5 kV multielectron beam lithography: MAPPER tool and resist process characterization

Río, David; Constancias, C.; Martı́n, M. Elena; Icard, B.; Nieuwstadt, J. van; Vijverberg, J.; Pain, Laurent

doi:10.1116/1.3517664

Cited by 25 publications

(17 citation statements)

References 20 publications

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“…The LETI currently works with the MAPPER pre-alpha tool, which uses 110 beams in parallel; 20 nm half pitch patterns were achieved with or without a chemically amplified resist. 5 These results confirm the potential of this technology.…”

Section: Introductionsupporting

confidence: 89%

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Pauliac-Vaujour

Brianceau

Comboroure

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.

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Section: Introductionsupporting

confidence: 89%

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Pauliac-Vaujour

Brianceau

Comboroure

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…The combined advantages of high resolution and reduced proximity effects make low-energy EBL an attractive alternative that may be useful for applications such as: bitpatterned media, nanoimprint molds, photomask manufacturing, and multiple-electronbeam lithography [7,9]. With its more efficient energy transfer, low-energy EBL is also useful when patterning ultra-thin and surface-sensitive materials [11].…”

Section: Discussionmentioning

confidence: 99%

“…This range of resolution is not sufficient for applications that require high throughput and high pattern resolution, such as photomask fabrication and multipleelectron-beam lithography for integrated circuits [7,9]. The key challenges to achieving high resolution at low electron energies are the reduced electron range, the increased broadening of the incident beam (forward-scattering), and larger minimum spot size.…”

mentioning

confidence: 99%

“…However, EBL at these high energies suffers from long-range proximity effects. Low-energy (sub-5 keV) EBL exhibits five key advantages over EBL at higher energies: (1) reduced dwell-time required for exposure (due to a higher resist sensitivity with only slightly reduced beam current) [5,6,7]; (2) lower system cost and a smaller footprint [7,8,9]; (3) significant reduction in long-range proximity effects [5,7,10]; (4) lower probability of sample damage and substrate heating [9]; and (5) more efficient delivery of energy into ultra-thin resists and self-assembled monolayers [11].…”

mentioning

confidence: 99%

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Sub-5keV electron-beam lithography in hydrogen silsesquioxane resist

Manfrinato

Cheong

Duan

et al. 2011

Microelectronic Engineering

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Abstract:We fabricated 9 to 30 nm half-pitch nested Ls and 13 to 15 nm half-pitch dot arrays, using 2 keV electron-beam lithography with hydrogen silsesquioxane (HSQ) as the resist. All structures with 15 nm half-pitch and above were fully resolved. We observed that the 9 and 10-nm half-pitch nested L's and the 13-nm-half-pitch dot array contained some resist residues. We obtained good agreement between experimental and Monte-Carlo-simulated point-spread functions at energies of 1.5, 2, and 3 keV. The longrange proximity effect was minimal, as indicated by simulated and patterned 30 nm holes in negative-tone resist.

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“…Maskless electron beam (EB) lithography by massively parallel writing has a great potential for the cost reduction of small-to-medium volume LSIs. As one of high throughput EB lithography systems [1][2][3], we proposed a massively parallel EB lithography (MPEBL) system using a nanocrystalline Si (nc-Si) emitter array integrated with an active-matrix driver LSI [1]. The nc-Si ballistically emits EB with excellent straightness at CMOS-compatible voltage, and the active-matrix driven emitter array in a large scale (e.g.…”

Section: Introductionmentioning

confidence: 99%

Development of MEMS pierce-type nanocrystalline Si electron-emitter array for massively parallel electron beam direct writing

Yoshida

Kojima²,

Ikegami

et al. 2014

2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS)

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This paper mainly reports the process development of a Pierce-type nanocrystalline Si (nc-Si) electron emitter array for massively parallel electron beam (EB) lithography based on active-matrix operation using a large-scaled integrated circuit (LSI). The emitter array consists of 100×100 hemispherical emitters formed by isotropic wet etching of Si. EB resist patterning was demonstrated by 1:1 projection exposure using a discrete emitter array at CMOS-compatible operation voltages. To independently control each emitter using the LSI, isolation trenches filled with benzocyclobutene (BCB) were fabricated in the Si substrate. In addition, the integration process of the emitter array, the LSI and an extraction electrode plate was developed based on Au-In and polymer bonding technologies.

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5 kV multielectron beam lithography: MAPPER tool and resist process characterization

Cited by 25 publications

References 20 publications

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Sub-5keV electron-beam lithography in hydrogen silsesquioxane resist

Development of MEMS pierce-type nanocrystalline Si electron-emitter array for massively parallel electron beam direct writing

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