5G-and-Beyond Scalable Machines

Fettweis, Gerhard; Matúš, Emil; Wittig, Robert; Hasler, Mattis; Damjancevic, Stefan A.; Nam, Seungseok; Haas, Sebastian

doi:10.1109/vlsi-soc.2019.8920308

Cited by 5 publications

(4 citation statements)

References 16 publications

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“…Today we rely on exactly this approach for implementing ML efficiently. For 6G we will have to find an equivalent solution by designing domain specific machines [40,41] which complement today's COTS servers and AI engines.…”

Section: Energy Efficient Wireless Network Control and Federated Learmentioning

confidence: 99%

Towards 6G wireless communication networks: vision, enabling technologies, and new paradigm shifts

You

Wang

Huang

et al. 2020

Sci. China Inf. Sci.

Self Cite

1,325

495

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The fifth generation (5G) wireless communication networks are being deployed worldwide from 2020 and more capabilities are in the process of being standardized, such as mass connectivity, ultra-reliability, and guaranteed low latency. However, 5G will not meet all requirements of the future in 2030 and beyond, and sixth generation (6G) wireless communication networks are expected to provide global coverage, enhanced spectral/energy/cost efficiency, better intelligence level and security, etc. To meet these requirements, 6G networks will rely on new enabling technologies, i.e., air interface and transmission technologies and novel network architecture, such as waveform design, multiple access, channel coding schemes, multi-antenna technologies, network slicing, cell-free architecture, and cloud/fog/edge computing. Our vision on 6G is that it will have four new paradigm shifts. First, to satisfy the requirement of global coverage, 6G will not be limited to terrestrial communication networks, which will need to be complemented with non-terrestrial networks such as satellite and unmanned aerial vehicle (UAV) communication networks, thus achieving a space-air-ground-sea integrated communication network. Second, all spectra will be fully explored to further increase data rates and connection density, including the sub-6 GHz, millimeter wave (mmWave), terahertz (THz), and optical frequency bands. Third, facing the big datasets generated by the use of extremely heterogeneous networks, diverse communication scenarios, large numbers of antennas, wide bandwidths, and new service requirements, 6G networks will enable a new range of smart applications with the aid of artificial intelligence (AI) and big data technologies. Fourth, network security will have to be strengthened when developing 6G networks. This article provides a comprehensive survey of recent advances and future trends in these four aspects. Clearly, 6G with additional technical requirements beyond those of 5G will enable faster and further communications to the extent that the boundary between physical and cyber worlds disappears.

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Section: Energy Efficient Wireless Network Control and Federated Learmentioning

confidence: 99%

Towards 6G wireless communication networks: vision, enabling technologies, and new paradigm shifts

You

Wang

Huang

et al. 2020

Sci. China Inf. Sci.

Self Cite

1,325

495

View full text Add to dashboard Cite

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“…Whereas, the total number of LD/ST operations is proportional to the square size of the matrix while the computation is O(n 3 ). Therefore, a decreasing in the percentage of LD/ST cycles from/to the memory to the total computing cycles n cycles has occurred which increases the computing performance based on equation (2). Similarly, reducing the fixed-point data size from 32-bit to 16-or 8-bit decreases LD/ST cycles from/to the data memory.…”

Section: B Design Scalability and Computing Performancementioning

confidence: 99%

“…Current and future applications in domains like deep neural network or next-generation cellular standards like 5G impose high demands on a novel approach for hardware platforms that can cope with high computational complexity and memory requirements with low energy consumption [1], [2]. Therefore, multi-/many-core architectures have emerged as adequate scalable hardware platforms to address…”

Section: Introductionmentioning

confidence: 99%

“…verification, validation, integration) and therefore the rising of development time and costs. Moreover, the design specifications could vary due to different application requirements which lead to the necessity of a new design process for each new application requirement [2]. Resultantly increasing the design effort and therefore time to market with a continuous inflation in non-recurring engineering costs.…”

Section: Introductionmentioning

confidence: 99%

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Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

2020

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Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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