6.3 105×65mm2 391Mpixel CMOS image sensor with &gt;78dB dynamic range for airborne mapping applications

Bogaerts, Jan; Lafaille, Raf; Borremans, M.; Jia, Guo; Ceulemans, Bart; Meynants, Guy; Sarhangnejad, Navid; Arsinte, Gavril; Statescu, Victor; Groen, Sonja van der

doi:10.1109/isscc.2016.7417933

Cited by 16 publications

(8 citation statements)

References 1 publication

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“…In 2D CMOS image sensors, a high resolution implies a larger pixel array and a larger chip area. To provide a short settling time for the signals transmitted on the pixel array’s row control bus, row driver circuits are generally designed on both sides of the pixel array [ 5 , 6 , 7 ].…”

Section: Introductionmentioning

confidence: 99%

“…As a result, the signal settling time is long, limiting the readout speed of the image sensor. This makes the frame rate of the very-large-pixel-array image sensor only a few frames per second [ 7 , 16 , 17 ]. Using the TX signals on the left and right sides of the pixel array as an example, inconsistencies in the row driver output signals on both sides of the pixel array will affect the frame rate.…”

Section: Introductionmentioning

confidence: 99%

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Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

Liu,

Guo,

Cheng

et al. 2024

Sensors

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With the application of stitching technology in large-pixel-array CMOS image sensors, the problem of non-synchronized output signals from pixel array bilateral driver circuits has become progressively more serious and has led to the DC perforation of bilateral driver circuits, while conventional clock tree synchronization design methodology does not apply to stitching technology. Therefore, this paper analyses reasons for the inconsistency in the output signals of bilateral driving circuits and proposes a synchronous driving method applicable to stitching pixel arrays based on the idea of on-chip output signal delay detection and calibration. This method detects and corrects the non-synchrony of the row driver output signals on both sides according to changes in the operating environment of the chip. This method is characterized by a simple structure and high reliability. Finally, based on the 55 nm stitching process, simulations are carried out in a CMOS image sensor with a chip area of 77 mm × 84 mm to verify that this method is feasible. This large image sensor with a 150 M pixel array has a frame rate of over 10 FPS.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

Liu,

Guo,

Cheng

et al. 2024

Sensors

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show abstract

“…The larger the array size, the smaller the capacity of the driver. Traditional driving technology can no longer meet the needs of large array [12,13,14,15,16,17]. Perhaps the frame rate of references is only a few frames, which is closely related to this factor.…”

Section: Introductionmentioning

confidence: 99%

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Guo

2020

IEICE Electron. Express

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A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm 2. The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

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“…In scientific imaging, medical imaging and advanced machine vision image systems, CMOS image sensors require higher and higher resolution, array size and pixel number [12][13][14][15][16][17][18][19][20]. However, the large array will produce large parasitic resistance and capacitance, which will reduce the integration of the chip and the readout speed of the signal.…”

Section: Introductionmentioning

confidence: 99%

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Guo

2020

IEICE Electron. Express

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The non-ideal factors and error sources of segmented DAC for multi-channel large array CMOS image sensor are given. An improved precise segmented DAC using adaptive switching technology is proposed. This scheme has been verified on a 50mm×50mm large array CMOS image sensor prototype chip, which consisting of 8320× 8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The measurement results show that the DNL of DAC can be reduced from 33 LSBs of traditional structure to within 0.5LSB, and the large array sensor chip reaches a high intrinsic dynamic range of 75dB, a low FPN of 0.06%, and a low photo response nonuniformity of 1.5% respectively. Finally, a good raw image is taken by the prototype sensor.

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6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications

Cited by 16 publications

References 1 publication

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

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