6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers

Lee, Youngjoo; Yoo, Hyung-Joun; Yoo, Injae; Park, In-Cheol

doi:10.1109/isscc.2012.6177075

Cited by 54 publications

(42 citation statements)

References 4 publications

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“…BCH codes are widely used in today's flash controllers to detect and correct multi-bit errors [28] [29]. Out of n total bits in a code word, the first k bits are data bits, and the remaining (n-k) bits are the error correction information to protect the data bits.…”

Section: Minimizing the Error Correction Latencymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

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Abstract-Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age -the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

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Section: Minimizing the Error Correction Latencymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

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“…BCH codes [11] are the most widely used due to their powerful error-correction capability. Choi [3] and Lee [4] implemented 16-bit and 32-bit BCH codes for flash memory respectively. We extensively compare FCR to different-strength BCH codes in this work, showing that FCR provides higher lifetime at much lower complexity.…”

Section: Related Workmentioning

confidence: 99%

“…Thus, there is a significant gap between the available (~3k P/E cycles) and desired (>50k P/E cycles) endurance of flash cells. One way to improve flash lifetime is to use stronger error correction codes (ECC) [3] [4]. Stronger ECC detects and corrects raw bit errors that happen over the lifetime of a flash cell, thereby increasing the number of P/E cycles each cell can tolerate without exposing the raw bit errors to the user.…”

Section: Introductionmentioning

confidence: 99%

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

Cai

Yalcin

Mutlu

et al. 2012

2012 IEEE 30th International Conference on Computer Design (ICCD)

203

267

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Abstract-With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46x average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.

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“…In 1960s Dr. Gallager invented LDPC codes [15], in which two innovative ideas were exploited: iterative decoding and constrained random code construction.…”

Section: Low-density Parity-check (Ldpc) Codesmentioning

confidence: 99%

BCH and LDPC Error Correction Codes for NAND Flash Memories

Marelli¹,

Micheloni²

2016

3D Flash Memories

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Nowadays NAND Flash memories are part of our lives in many ways. The storage world is a completely new world thanks to NAND. As a matter of fact, it wouldn't be possible to have a smartphone without the use of NAND memories as the storage media. After USB keys and digital cameras, Solid State Drives (SSDs) are now the new disruptive application for Flash. Consumer-class ultra-light and ultra-thin laptops require NAND storage, but it is really in the cloud and in enterprise servers that the use of NAND can be a paradigm shift.Because NAND devices can't be manufactured without defects, the use of Error Correction Codes (ECCs) has always been a common practice. While BCH (Bose-Chaudhuri-Hocquenghem) is a de facto standard for consumer applications, LDPC (Low-Density-Parity-Check) codes are a typical choice in the enterprise world. This is especially true when looking at planar (2D) ultra-scaled (e.g. 15 nm) NAND. Generally speaking, LDPC offers higher correction capabilities, but BCH remains a good solution when bandwidth requirements are very stringent.As discussed in previous chapters, 3D NAND is becoming a reality in the market. In terms of noise models, 2D and 3D have some commonalities: they are both very complex and they change during the NAND's lifetime! We do expect 3D NAND to bring new failure models into the game; all the scientists working on ECCs for non-volatile memories will have to put their best effort for getting as close as possible to the Shannon limit.To set the stage, in this chapter we cover both BCH and LDPC codes. After a brief introduction, we will see the implementation issues when coupling these codes with a "real" NAND communication channel; practical workarounds will also be discussed.

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6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers

Cited by 54 publications

References 4 publications

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

BCH and LDPC Error Correction Codes for NAND Flash Memories

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