6-Gb/s serial link transceiver for NoCs

Mohammed, Safaa A.; Ibrahim, Sameh A.; Habib, S. E. D.

doi:10.1109/icecs.2015.7440339

Cited by 1 publication

(1 citation statement)

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“…previous WiNoC literature rarely details information about these blocks. Therefore, we propose to adopt a SER/DESER binary MUX tree topology with half-rate architecture [30], [31], which uses a 625 MHz half-rate clock source to generate 1.25 Gb/s data rate. In addition, this architecture is a good compromise between higher data rates and risks of duty-cycle distortion and clock skew.…”

Section: B Wireless Interface Architecturementioning

confidence: 99%

A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment

Sosa¹,

Sentieys

Roland

2018

2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)

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Wireless Network-on-Chip (WiNoC) is one of the most promising solutions to overcome multi-hop latency and high power consumption of modern many/multi core System-on-Chip (SoC). However, the design of efficient wireless links faces challenges to overcome multi-path propagation present in realistic WiNoC channels. In order to alleviate such channel effect, this paper presents a Time-Diversity Scheme (TDS) to enhance the reliability of on-chip wireless links using a semi-realistic channel model. First, we study the significant performance degradation of state-of-the-art wireless transceivers subject to different levels of multi-path propagation. Then we investigate the impact of using some channel correction techniques adopting standard performance metrics. Experimental results show that the proposed Time-Diversity Scheme significantly improves Bit Error Rate (BER) compared to other techniques. Moreover, our TDS allows for wireless communication links to be established in conditions where this would be impossible for standard transceiver architectures. Results on the proposed complete transceiver, designed using a 28-nm FDSOI technology, show a power consumption of 0.63mW at 1.0V and an area of 317 µm 2. Full channel correction is performed in one single clock cycle.

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Section: B Wireless Interface Architecturementioning

confidence: 99%