A report is presented on 100 nm and 200 nm InAs PHEMTs on an InP substrate with a record f T performance. This result was obtained by reducing a parasitic delay associated with the extrinsic gate capacitances of the device, as well as by using an InAs sub-channel to improve carrier transport properties. In particular, a 100 nm InAs PHEMT exhibits excellent performance, such as g m,max ¼ 2 S/mm, f T ¼ 421 GHz and f max ¼ 620 GHz at V DS ¼ 0.7 V. The device also shows a well-balanced f T and f max in excess of 400 GHz, even at V DS ¼ 0.5 V. In addition, the device gains about 70 % improvement in f T as L g shrinks down from 200 to 100 nm. The results obtained in this work should make this technology of great interest to a multiplicity of applications and guide a realistic path in trying to achieve a 1 THz f T from III-V HEMTs in the future.Introduction: Over the past three decades, gate length (L g ) scaling has been the key technology driver in III-V HEMTs with the InGaAs/ InAlAs material system to demonstrate record high frequency performance, as assessed by current-gain cutoff frequency (f T ) and maximum oscillation frequency (f max ). Recent reports on record high frequency characteristics of InGaAs/InAlAs HEMTs have been published with L g ¼ 30 -40 nm [1-3]. These improvements in RF performance have also arisen partly from the use of an indium-rich InAs sub-channel that increases the average electron velocity under the gate and improves charge control behaviour in the channel.Despite the record values that have been obtained for sub-100 nm InP HEMTs, clearly there exists scope for further improvement. In fact, the literature on record values of f T in III-V HEMTs reveals that only a 57 % improvement in f T is obtained by reducing L g from 130 nm [4] to 30 nm [1], indicating that the device suffers from an increased influence of parasitic delay terms and poor short-channel effects [5]. Without any doubt, the full benefit of L g scaling requires the minimisation of the delay associated with parasitic resistances and extrinsic gate capacitances, as L g scales down deeply. In particular, the parasitic delay due to the extrinsic fringing gate capacitance (C g,ext ) plays a more important role as L g shrinks, because the intrinsic gate capacitance (C gi ) scales down linearly with L g . In this Letter, we report that a systematic reduction of the parasitic delay associated with the extrinsic gate capacitance leads to an excellent high frequency performance in InAs PHEMTs on an InP substrate. In particular, our device exhibits a record f T ¼ 421 GHz at L g ¼ 100 nm and f T ¼ 250 GHz at L g ¼ 200 nm.