650V superjunction MOSFET using universal charge balance concept through drift region

Lee, Seung−Chul; Oh, Kwang-Hoon; Kim, Soo Seong; Yun, Chong Man

doi:10.1109/ispsd.2014.6855981

Cited by 12 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…BV Ron [16] 680 V 15.5 mΩ•cm 2 [17] 730 V 23 mΩ•cm 2 [18] 650 V 24.7 mΩ•cm 2 [19] 650 V 17 mΩ•cm 2 [20] 750 V 24.6 mΩ•cm 2 Proposed 700 V 17.5 mΩ•cm 2 The full structure of the 650-V SJ device designed in this work is schematically shown in Figure 2d. The device structure is divided into cell and terminal regions (with only one cell illustrated in the figure).…”

Section: Refmentioning

confidence: 99%

Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress

Tang

Chen

et al. 2022

Electronics

View full text Add to dashboard Cite

In this work, an anomalous thick oxide-degradation phenomenon in n-type 650-V class super-junction VDMOS transistors is investigated. An unexpected threshold voltage (Vt) decrease was observed with high positive bias temperature instability stress, and the saturation current (IDsat) increases with the stress time. Repeatable and reproducible behaviors have been achieved from multiple devices under test. Based on simulation and experimental results, it is found that the high-energy electrons (caused by high positive gate voltage) in the n-type region at the bottom of the gate oxide layer (top of the N-pillar) are injected into the gate oxide. The high-energy electrons generate electron-hole pairs during the transport to the anode, leaving holes in the gate oxide layer, and thus decreased Vt and increased IDsat. Finally, C-V measurement is also carried out which further confirms the above analysis.

show abstract

Section: Refmentioning

confidence: 99%

Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress

Tang

Chen

et al. 2022

Electronics

View full text Add to dashboard Cite

show abstract

“…This process is generally used in the SJ VDMOS with the V B of 30-100 V. It achieves the J-VSL length of 2.5-3 μm with the maximum implantation energy of 1.5-2 MeV. Furthermore, the energy of 25 MeV can also be used to realize the SJ with V B of 550 V, and the special mask with the difficult fabrication process is also needed [30] .…”

Section: Development Of the Processmentioning

confidence: 99%

Concept and design of super junction devices

Zhang

Qiao

et al. 2018

J. Semicond.

View full text Add to dashboard Cite

The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of Ron∝VB2.5, showing a quasi-linear relationship of Ron∝VB1.03.

show abstract