73ps si bipolar ECL circuits

Tang, D.D.; Li, G.P.; Chuang, Ching-Te; Danner, D. A.; Ketchen, M. B.; Mauer, J. L.; Smyth, M.; Manny, M.; Cressler, John D.; Ginsberg, B.J.; Petrillo, E.J.; Ning, T.H.; Hu, Chih-Chun; Pak, Haksong

doi:10.1109/isscc.1986.1156926

Cited by 13 publications

(1 citation statement)

References 2 publications

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“…The PPSEM is used here for the full characterization of waveforms at the internal nodes of sub-100-ps silicon bipolar ECL ring oscillators fabricated using a 1.2-pm double-poly self-aligned process [ 5 ] . The transistors in the basic gate shown in Fig.…”

Section: Circuit Measurement Results and Discussionmentioning

confidence: 99%

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

May

Halbout

Chuang

et al. 1988

IEEE Trans. Electron Devices

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This paper describes a noncontact waveform measurement technique for the characterization of high-speed LSI and VLSI circuits using a Picosecond Photoelectron Scanning Electron Microscope with 5-ps temporal resolution, 0.1-pm spatial resolution, and a voltage resolution of 3 m V / a . The capability of the technique to measure and monitor the internal waveforms and to resolve the different Contributions of the delay in the circuit without any loading effect is demonstrated by its application to the full characterization of sub-100-ps silicon bipolar ECL circuits.

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Section: Circuit Measurement Results and Discussionmentioning

confidence: 99%

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

May

Halbout

Chuang

et al. 1988

IEEE Trans. Electron Devices

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The Effect of Source and Drain Pocketing on the Performance of Double-Gate Tunnelling Field-Effect Transistor

Elgamal

2020

J. Phys.: Conf. Ser.

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In this paper the digital and analogue performance of double-gate tunnelling FET, DGTFET, is reported, when a pocket of different dielectric is inserted near the source, drain or both. The variation of these pocket lengths and their relative shift to the edge of source or drain region affects device performance. The investigated performance parameters include the ON/OFF ratio, the maximum cut-off frequency, fT, the subthreshold swing, SS, and the ambipolar current, Iambi. With the aid of TCAD simulator, the effect of pocket parameter variation is studied. Our study shows that when the main gate dielectric is hafnium dioxide, the source pocket is favored to be of low dielectric constant and high width. However, for the drain case, it is better to have shorter pockets with a low dielectric constant. The investigation shown here proves that pocketing the DGTFET can enhance its whole performance in terms of investigated parameters.

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Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

Hackbarth

Chen

1988

IEEE Trans. Electron Devices

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73ps si bipolar ECL circuits

Cited by 13 publications

References 2 publications

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

The Effect of Source and Drain Pocketing on the Performance of Double-Gate Tunnelling Field-Effect Transistor

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

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