The Effect of Source and Drain Pocketing on the Performance of Double-Gate Tunnelling Field-Effect Transistor

Abstract

In this paper the digital and analogue performance of double-gate tunnelling FET, DGTFET, is reported, when a pocket of different dielectric is inserted near the source, drain or both. The variation of these pocket lengths and their relative shift to the edge of source or drain region affects device performance. The investigated performance parameters include the ON/OFF ratio, the maximum cut-off frequency, fT, the subthreshold swing, SS, and the ambipolar current, Iambi. With the aid of TCAD simulator, the effect of pocket parameter variation is studied. Our study shows that when the main gate dielectric is hafnium dioxide, the source pocket is favored to be of low dielectric constant and high width. However, for the drain case, it is better to have shorter pockets with a low dielectric constant. The investigation shown here proves that pocketing the DGTFET can enhance its whole performance in terms of investigated parameters.

Optimization for Device Figure of Merit of Ferroelectric Tunnel FET using Genetic Algorithm

“…[1][2][3][4][5][6][7][8][9][10] After observation and experimental verification of negative capacitances (NC) in ferroelectric materials (Fe), subthreshold swing based research and development has been taken seriously by semiconductor research community. [10][11][12][13][14][15] The ferroelectric materials based research&development, [11][12][13][14][15][16] provides a big domainto overcome the classical limitations [17][18][19][20][21][22] of conventional CMOS technology for low power. The non-identical polarization entire-near conventional dielectric, help to boost up the electricbeyond the end of the silicon roadmap.…”

“…This indicates optimization is needed for desirable design. Genetic algorithm found suitable used for optimization.In thisresearchwork, we have used genetic algorithm (GA) for optimization of desirable device design parameters like I ON , SS, I amb [17][18][19][20][21][22][23][24][25][26][27][28] for ferroelectric tunnel FET.…”