Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

Li, G.P.; Hackbarth, E.; Chen, T.-C.

doi:10.1109/16.2420

Cited by 66 publications

(4 citation statements)

References 19 publications

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“…Previously (3], we pointed out that the "drain corner" tunneling occurs at lower voltage than that a.cross the junction area., a. fact that has received considerable attention [23]. For the present study, I will use Equation 9 .10 for area tunneling, both for simplicity and because I expect considerable cleverness on the part of process designers as this phenomenon becomes limiting.…”

Section: Io·' 10°mentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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Section: Io·' 10°mentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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“…3 in the energy bands. 9 Since the hole contribution is determined by the BE bias alone, the BC junction can be biased so that the contribution from the electrons dominates the FC stress. The OC stressing is a constant voltage method.…”

Section: Methodsmentioning

confidence: 99%

Current gain degradation in SiGe HBTs by hot carriers

Gill

McAlister

Storey

et al. 2002

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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The effects of open-collector and forward-collector reverse bias stressing on SiGe HBTs have been studied. Increases in the base current and degradation of the current gain, similar to those found in pure Si BJTs, were observed in the stressed devices. Short periods of severe reverse base-emitter bias stress cause random telegraph signals to occur in the base current. Damage is caused by hot holes, created by band-to-band tunneling in the base-emitter junction, during open-collector stressing and by hot holes and electrons, injected from the collector into the base, in forward-collector stressing. A comparison of the charge to failure as a function of stress voltage between the two hot carrier stressing methods suggests that, at a given kinetic energy, holes cause more damage than electrons.

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“…Reverse-bias tunneling in heavily doped eb diodes has been investigated, for example, in [39,43,44]' using polysilicon-contacted bipolar transistors with different base implant dosesY In [39], aligned eb configurations were investigated together with self-aligned configurations in order to exclude sidewall diode effects, which are frequently observed in self-aligned bipolar transistors [41]. For a given reverse-bias voltage, the measured current density of the aligned samples scaled with the emitter area and showed a strong increase with the base implant dose, as is expected for interband tunneling.…”

Section: Reverse-bias Currents Breakdownmentioning

confidence: 99%

Physics and Modeling of Bipolar Junction Transistors

Reisch

2003

High-Frequency Bipolar Transistors

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Physics-based compact models provide insight into the relations between the layout, doping profiles and electrical parameters and therefore form a language for communication between process development and circuit design. This chapter looks at the physics of modern integrated bipolar junction transistors with particular emphasis on the derivation of closed-form expressions for their terminal behavior, which are required for the formulation of compact models. On the basis of these results, the most prominent compact models for large-signal and small-signal operation will be considered, together with a presentation of parameter extraction procedures.

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Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

Cited by 66 publications

References 19 publications

Scaling of MOS technology to submicrometer feature sizes

Scaling of MOS technology to submicrometer feature sizes

Current gain degradation in SiGe HBTs by hot carriers

Physics and Modeling of Bipolar Junction Transistors

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