8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm<sup>2</sup>, 1mm Package-on-Package

Gomes, Wilfred; Khushu, Sanjeev; Ingerly, D.; Stover, Patrick; Chowdhury, Nasirul; O'Mahony, Frank; Balankutty, Ajay; Dolev, Noam; Dixon, Martin; Jiang, Lei; Prekke, Surya; Patra, Biswajit; Rott, Pavel V.; Kumar, Rajesh

doi:10.1109/isscc19947.2020.9062957

Cited by 59 publications

(8 citation statements)

References 3 publications

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“…The Lakefield mobile processor also adopted multiple Chiplets design technology, which consists of the computing and memory Chiplets prepared with optimal technology (10 nm and 22 FFL). All Chiplets were bonded face to face with micro-bumps in 50 µm pitch (Foveros technology) [31]. The parasitic capacitance and resistance are below 250 fF and 70 mΩ, respectively.…”

Section: Computing Architecture Integrated With 3d Technologymentioning

confidence: 99%

Architecture of Computing System based on Chiplet

et al. 2022

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Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

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Section: Computing Architecture Integrated With 3d Technologymentioning

confidence: 99%

Architecture of Computing System based on Chiplet

et al. 2022

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“…This approach can be further classified by the underlying technology, with the main ones being: 1) through-silicon via (TSV)-based 3D ICs, 2) face-to-face (F2F) 3D ICs, 3) monolithic 3D (M3D) ICs [15]. Various studies, prototypes, and commercial products have shown that native 3D integration can indeed offer significant benefits over conventional 2D ICs, e.g., see [16], [17].…”

Section: 5d and 3d Integrationmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

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“…Heterogeneous 3D IC design is an extremely useful approach that provides a wide array of possibilities in power and performance improvements using a high-performance technology on one die, and low-power technology on the other. Block-level face-to-face integrated heterogeneous 3D IC processor has recently been taped-out [9] by Intel using Foveros 3D-integration [10]. Exploring heterogeneous integration at the finer gate-level integration with monolithic 3D ICs would be of an extreme importance, and is supported for the first time with Pin-3D.…”

Section: Benefits Of Pin-3d Optimizermentioning

confidence: 99%