8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor

Zhang, Yiqun; Khayatzadeh, Mahmood; Yang, Kaiyuan; Saligane, Mehdi; Pinckney, Nathaniel; Alioto, Massimo; Blaauw, David; Sylvester, Dennis

doi:10.1109/isscc.2016.7417956

Cited by 52 publications

(25 citation statements)

References 5 publications

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“…Second, to evaluate the comparison with previous EDAC technique, an EDAC processor is proposed. It employs the latest razor-style circuits [5] to detect timing error and correct it by error mask method. For fair comparison, it still needs to insert clock gate in the non-critical paths.…”

Section: Sgerc Processor Implementationmentioning

confidence: 99%

“…[3] proposes double-sampling design to detect timing error by adding additional memory elements and [4] is based on the transition detector. Recently, iRazor [5] uses only three-transistor current-sensing circuit to detect timing violation and adopts error mask technique to recover with one-cycle penalty. For timing error correction, error mask technique has a better performance and can be realized without the modification of processor architecture compared with the previous replay mechanism [6].…”

Section: Introductionmentioning

confidence: 99%

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SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

Zhu

Xiang

Chen

et al. 2017

IEICE Electron. Express

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This paper presents a self-gated error resilient cluster of sequential cells (SGERC) to sample the critical data in wide-voltage operation for EDAC system. SGERC introduces latch-based clock gating technique to error resilient circuits and proposes a customized clock gate which has the ability of timing error self-correction with only two additional transistors added for the first time. Further, it totally eliminates the timing error detection circuits required by each critical register before and utilizes the data-driven clock gating circuits to generate timing error information. Simulation results show that SGERC design achieves 58.3% energy efficiency improvement compared with the baseline design and 19.4% over the latest EDAC design.

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Section: Sgerc Processor Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

Zhu

Xiang

Chen

et al. 2017

IEICE Electron. Express

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“…A representative on-line timing error detection circuits is the Razor flip-flop [3,4,5,11,12]. Since the timing error is detected after the system is incorrect, error correction is mandatory.…”

Section: Related Workmentioning

confidence: 99%

“…Since the timing error is detected after the system is incorrect, error correction is mandatory. Generally, error correction methods include instruction replay at halved clock frequency [5], counterflow pipelining [11], clock gating [3,6], and so on. However, the above error correction scenarios incur large performance loss.…”

Section: Related Workmentioning

confidence: 99%

“…However, adding adequate timing margin leads to the performance loss and overhead of area and energy, especially in deep sub-micrometer CMOS technology node. On-line Error Detection and Correction (EDC) has proved to be a promising technique to mitigate the redundant timing margin [3]. The prototype of the EDC system is Razor circuit which detects the timing error then corrects it [4,5,6].…”

Section: Introductionmentioning

confidence: 99%

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TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor

Yong

Xiang

Meng

et al. 2016

IEICE Electron. Express

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Abstract:Recently, large efforts are made to achieve high throughput for aggressive voltage/frequency scaling in Error Detection and Correction system. In this paper, a zero-cycle penalty Timing-Borrowing and Clock Token (TBCT) based error correction method is proposed. A new error masking flip-flop is designed to enable time-borrowing and a clock token system is provided to pay back the borrowed time by locally shifting the clock phase of vulnerable flip-flops on the cascaded pipeline. The TBCT error correction method and error masking flip-flop are implemented into a 3-stage industrial Chinese microprocessor in a 40 nm CMOS process. Final experiment results show the proposed method achieves 1%-6% higher throughput than clock gating method and 9%-41% higher throughput than instruction replay.

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A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring

Sai

Zwoliński

Halak

2019

Ageing of Integrated Circuits

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8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor

Cited by 52 publications

References 5 publications

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor

A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring

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