8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

Matsuo, Shin’ichiro; Bales, Tim; Shoda, Makoto; Osawa, Shinji; Kawamura, Katsuyuki; Andersson, Alexandra; Haque, Munirul; Honda, Hidenari; Almond, B.; Mo, Yaowu; Gleason, J.; Chow, T.W.; Takayanagi, Isao

doi:10.1109/ted.2009.2030649

Cited by 83 publications

(48 citation statements)

References 14 publications

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“…This ADC migration to as close as from the detector as possible increases digital parallelism. Different ADC architectures, from slower slope ADC to faster SAR-ADCs (Matsuo et al, 2009) and sigma-delta ADCs are also used to increase the total output throughput. Multiple-inputs, multiple-outputs (MIMO) approach is also used to alleviate the bottleneck speed limitation but the output/input ratio is still very close to one as in MISO CIS case.…”

Section: Page 6 Of 13 Sensor Reviewmentioning

confidence: 99%

Advances on CMOS image sensors

Gouveia

Choubey

2016

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This paper offers an introduction to the technological advances of image sensors designed using complementary metal-oxide-semiconductor (CMOS) processes along the last decades. We review some of those technological advances and examine potential disruptive growth directions for CMOS image sensors and proposed ways to achieve them. Those advances include breakthroughs on image quality such as resolution, capture speed, light sensitivity and color detection and advances on the computational imaging. The current trend is to push the innovation efforts even further as the market requires higher resolution, higher speed, lower power consumption and, mainly, lower cost sensors. Although CMOS image sensors are currently used in several different applications from consumer to defense to medical diagnosis, product differentiation is becoming both a requirement and a difficult goal for any image sensor manufacturer. The unique properties of CMOS process allows the integration of several signal processing techniques and are driving the impressive advancement of the computational imaging. With this paper, we offer a very comprehensive review of methods, techniques, designs and fabrication of CMOS image sensors that have impacted or might will impact the images sensor applications and markets.

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Section: Page 6 Of 13 Sensor Reviewmentioning

confidence: 99%

Advances on CMOS image sensors

Gouveia

Choubey

2016

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“…Table 2 summarizes power consumption of the full resolution mode operating at 80fps. Compared to the previously developed 8.9M-pixel 60fps image sensor 5) fabricated in the same process technology, we have achieved double the readout rate with little increase of power consumption (1085mW vs. 1120mW). There are several formulae to represent an image sensor's figure of merit (FOM) 7) .…”

Section: Fabrication and Characterizationmentioning

confidence: 92%

[Paper] A 1-inch Optical Format, 80fps, 10.8Mpixel CMOS Image Sensor Operating in a Pixel-to-ADC Pipelined Mode

Takayanagi¹,

Yoshimura²,

Sato³

et al. 2014

MTA

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“…It is only 3% of a conventional binary weighted 9-bit DAC. than DNL for imager sensor applications because of the noise and the non-linearity from the pixel sensor [14].…”

Section: Static Performance Measurements-effectiveness Of Overlappingmentioning

confidence: 99%

“…Table 1 summarizes the performance of this work and other related works used in CMOS imager sensors. Multiple-ramp Single-slope (MRSS) and 2-step Single-slope (2-step SS) ADCs feature in small channel area and low power [1,2]; SAR ADCs are highly power efficient [14]; cyclic ADCs perform high-resolution at fast conversion speed [15]. To assist a uniform comparison across different topologies, the throughput per unit time per unit chip area in bits (Mbit=ðs Â mm 2 Þ) for each reported ADC is measured.…”

Section: Performance Summary and Comparisonmentioning

confidence: 99%

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

Wang

Salthouse

2015

Microelectronics Journal

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a b s t r a c tThe Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC's 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from þ 5.14/ À1 LSB to þ 1.27/ À 0.92 LSB, and improved the INL error from þ 5.35/À 5.34 LSB to þ 3.17/À 3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.& 2015 Elsevier Ltd. All rights reserved. MotivationColumn-parallel ADCs are frequently used in CMOS imagers to achieve fast frame rates. The key parameters for the design of these ADCs include area, pitch, speed, and quantization resolution. The single-slope architecture is often used because of the simple circuitry in each channel. But the conversion rate for this type of ADC is usually less than 1 MSPS, because the full-scale conversion time doubles with each additional bit [1,2]. In comparison, successive approximation register (SAR) ADCs can perform faster conversions at moderate to high resolution because the conversion time scales linearly with the number of bits. The disadvantage of SAR ADCs, however, is that they rely on a DAC to produce reference voltages. Usually a high-resolution high-linearity SAR ADC requires a large silicon area for capacitors in the DAC, making it unsuitable for column-parallel applications.One way to mitigate the large area requirement of SAR ADCs is to use the subranging technique. First a coarse conversion is performed to determine the M most significant bits. Then a fine conversion is performed over the subrange determined by the coarse conversion to calculate the K least significant bits. One way of implementing this second conversion is using a capacitor-array DAC to resolve voltages between two reference voltages that are generated with a resistor ladder [3]. When building an array of column-parallel ADCs, this resistor ladder can be shared by all of the channels. The area can be further reduced by using the same capacitor-array DAC to perform both the coarse and fine conversions, but in order to guarantee a correct coarse conversion for any inputs, the DAC must be accurate to the full resolution of the conversio...

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8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

Cited by 83 publications

References 14 publications

Advances on CMOS image sensors

Advances on CMOS image sensors

[Paper] A 1-inch Optical Format, 80fps, 10.8Mpixel CMOS Image Sensor Operating in a Pixel-to-ADC Pipelined Mode

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

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