84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5‐tap FFE

Abstract

The increasing demand for bandwidth fuels the development towards high data rate electrical serial links. These links generally suffer from considerable frequency-dependent loss, introducing the need for equalisation at 10 Gbit/s and higher. Modulation schemes with improved spectral efficiency, with respect to non-retrun to zero (NRZ), combined with feed-forward equalisation (FFE), allow increasing the chip-to-chip data rate with the drawback of a more complex, e. g. multi-level, receiver (Rx). The use of duobinary modulation (DB) is presented to realise a high-speed serial link. The increase in complexity of a DB Rx is limited, whereas the required channel bandwidth compared with NRZ is reduced. Furthermore, the need for equalisation when compared with PAM4 is reduced as the required roll-off that is needed to create a duobinary modulated signal from an NRZ stream can incorporate the frequency-dependent loss of the link.Introduction: In this Letter, a transmitter (Tx) and receiver (Rx) chipset targeting a serial data rate beyond 80 Gbit/s is presented. A block diagram of the complete transceiver chain is shown in Fig. 1. The Tx consists of a 4:1 multiplexer (MUX) connected to a 5-tap feed-forward equalisation (FFE) with an approximate delay of 12.5 ps between the taps. Together with the channel, the FFE creates an equivalent channel that transforms the NRZ from the MUX into duobinary at the Rx input (Fig. 1). The Rx chip includes a duobinary front-end connected to a 1:4 demultiplexer (DEMUX). A data rate of 84 Gbit/s is achieved across a differential link, which includes a parallel pair of 10 cm coaxial cables and the 5 cm grounded coplanar waveguide traces on the chip test boards. We believe this to be the fastest reported electrical duobinary transmission experiment to date [1]. The Tx and Rx chips are fabricated in 130 nm STMicroelectronics SiGe bipolar CMOS (BiCMOS) 9 MW technology and are mounted directly onto the printed circuit board (PCB) substrate using thermosonic flip-chip bonding. Serial peripheral interface (SPI) is used to control both chips and to adjust the bias currents, the comparison levels of the Rx, the tap weights of the FFE and the clock delays in the MUX and DEMUX.

40-Gb/s TDM-PON Downstream Link With Low-Cost EML Transmitter and APD-Based Electrical Duobinary Receiver

“…10 that the duobinary precoder is omitted from the experimental setup, not only when using the NRZ modulation format, but also in the case of EDB; this is because the precoder operating on the PRBS signal yields a delayed version of the PRBS signal [20]. As such, the precoder can be simply removed when using PRBS data [4]- [8], [20]. Fig.…”

“…The EDB decoder [20] combines a 3-level signal decoding function and a 1 ÷ 4 deserializer. The TIA output signal is compared to two configurable threshold levels.…”

Real-Time 100 Gb/s Transmission Using Three-Level Electrical Duobinary Modulation for Short-Reach Optical Interconnects

“…To decode the EDB signal, the receiver presented in [16] is used. The EDB decoding scheme is given at the bottom of Fig.…”

“…The EDB RX IC consists of a transimpedance (TIA) input stage with a bandwidth of 41 GHz, two parallel level-shifting limiting amplifiers, an XOR stage and a 1-to-4 DEMUX. The decoding and DEMUX operation are combined to interleave the decoding step [16], significantly reducing power consumption. The EDB RX can be re-configured into an NRZ RX with four demuxed outputs.…”

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

“…At the receiver, the signal is amplified and both eyes are extracted as explained in section II. After a XOR and demultiplexing stage (more details in [18]), four quarter-rate streams are obtained. Due to the absence of CDR circuitry in the receiver prototype, the decision clock of the receiver is a delayed version of the transmitter clock.…”