90nm low leakage SoC design techniques for wireless applications

Royannez, Philippe; Mair, Hugh; Dahan, Franck; Wagner, M.; Streeter, M.; Bouetel, L.; Blasquez, J.; Clasen, H.; Semino, G.; Dong, J.; Scott, David B.; Pitts, B.; Raibaut, C.; Ko, Uming

doi:10.1109/isscc.2005.1493907

Cited by 76 publications

(32 citation statements)

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“…A cell library specific to power gating needs to be designed to accommodate the requirement of additional power networks [1], [5]. The location of current switches and power-gating specific cells, such as state retention storage elements, is limited [8]- [10], and severely constrains the placement of logic cells. These problems are, in essence, due to the heterogeneous requirement on power networks.…”

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confidence: 99%

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

Kim

Shin

2007

IEEE Trans. Circuits Syst. II

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Abstract-The application of power gating to cell-based semicustom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-m CMOS technology.

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confidence: 99%

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

Kim

Shin

2007

IEEE Trans. Circuits Syst. II

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“…The results show that the proposed PG structure is a practicable solution for high energy reduction in ultra-low voltage nanoscale CMOS circuits. [3], Two-pass PG [4], Zigzag PG [5], and Selective PG [6]) cannot be used due to the impractical delay increase and long wakeup time. …”

Section: Discussionmentioning

confidence: 99%

Power gating for ultra-low voltage nanometer ICs

Kim

Nan

Choi

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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A novel power gating (PG) structure using seriesconnected low-V th power switches has been developed to extend the PG structure to the ultra-low voltage region while keeping low leakage power in sleep mode. The series-connected low-V th power switches induce a short wake-up time due to fast current discharge through the switches, whereas the PG structure can suffer from large gate tunneling leakage currents and wake-up rush-currents. Therefore, in this paper, extra circuitries are added to control the gate-tunneling leakage and rush-currents; however the total PG switch size of the proposed PG structure including the extra circuits is the same as the conventional one. The simulation results are compared to those of other wellknown PG schemes and show that, in the ultra-low voltage region, the other high-V th based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6V supply voltage which are designed using 45nm CMOS predictive technology model.

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“…Gammie et al [3] discuss 'SmartReflex' power management technology used by Texas Instruments mobile processors, such as 90nm OMAP2420 processor [141], 65 nm OMAP3430 processor [142] and the 45 nm 3.5 G Baseband and Multimedia Application Processor [143]. For saving both dynamic and leakage energy in SRAM, these processors use techniques such as state-preserving and state-destroying leakage control, voltage scaling etc.…”

Section: Cache Energy Saving In Real-world Chipsmentioning

confidence: 99%

A survey of architectural techniques for improving cache power efficiency

Mittal

2014

Sustainable Computing: Informatics and Systems

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90nm low leakage SoC design techniques for wireless applications

Cited by 76 publications

References 4 publications

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

Power gating for ultra-low voltage nanometer ICs

A survey of architectural techniques for improving cache power efficiency

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