930-V 170-m&amp;lt;tex&amp;gt;$Omega cdot hbox cm^2$&amp;lt;/tex&amp;gt;Lateral Two-Zone RESURF MOSFETs in 4H-SiC With NO Annealing

Wang, W.; Banerjee, Sneha; Chow, T. Paul; Gutmann, R.J.

doi:10.1109/led.2004.825196

Cited by 26 publications

(4 citation statements)

References 8 publications

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“…The device with the optimized dose design blocked 1080 V and showed a low on-resistance of 79 mΩcm 2 at a gate oxide field of 3.0 MV/cm on a p-type epilayer doped to 7×10 15 cm -3 . The figure-of-merit of this device (V B 2 /R on ) [6] reaches 14.8 MW/cm 2 , which is the best performance among lateral SiC MOSFETs reported (V B 2 /R on = 3-10 MV/cm 2 ) [3][4][5].…”

Section: Discussionmentioning

confidence: 76%

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Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Kawano

Kimoto

Suda

et al. 2005

MSF

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Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.

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Section: Discussionmentioning

confidence: 76%

“…The channel mobility that is extracted from non-RESURF MOSFETs on the same wafer was 20-25 cm 2 /Vs. These characteristics are the best performance for lateral SiC MOSFETs [3][4][5].…”

Section: Resultsmentioning

confidence: 95%

Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Kawano

Kimoto

Suda

et al. 2005

MSF

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“…The channel mobility was assessed by processing planar inversion-type MOSFETs on p-type epilayers doped to 1x10 16 cm -3 . Lateral high-voltage MOSFETs with a two-zone RESURF (Reduced Surface Field) structure [10,11] were also fabricated. Although the oxide formed by the "CVD + Ar anneal" process is leaky, N 2 O annealing resulted in significantly improved dielectric properties (resistivity: 10 16 Ωcm, breakdown field > 10 MV/cm).…”

Section: Methodsmentioning

confidence: 99%

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N<sub>2</sub>O Annealing

Kimoto

Kawano

Noborio

et al. 2006

MSF

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Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

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“…On the basis of the above studies, depicted in Fig. 3 (metal-oxide-semiconductor field-effect transistor) formed on the C( ) face using the pyrogenic oxidation [19] . The channel mobility of the device is 41 cm 2 /(V•s), surpassing the channel inversion layer mobility formed on the Si(0001) face.…”

Section: Crystal Orientation and Annealing Environmentsmentioning

confidence: 99%

Review of the SiC LDMOS power device

Hu,

Yao,

et al. 2024

J. Semicond.

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Silicon carbide (SiC), as a third-generation semiconductor material, possesses exceptional material properties that significantly enhance the performance of power devices. The SiC lateral double-diffused metal–oxide–semiconductor (LDMOS) power devices have undergone continuous optimization, resulting in an increase in breakdown voltage (BV) and ultra-low specific on-resistance (R on,sp). This paper has summarized the structural optimizations and experimental progress of SiC LDMOS power devices, including the trench-gate technology, reduced surface field (RESURF) technology, doping technology, junction termination techniques and so on. The paper is aimed at enhancing the understanding of the operational mechanisms and providing guidelines for the further development of SiC LDMOS power devices.

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930-V 170-m<tex>$Omega cdot hbox cm^2$</tex>Lateral Two-Zone RESURF MOSFETs in 4H-SiC With NO Annealing

Cited by 26 publications

References 8 publications

Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N<sub>2</sub>O Annealing

Review of the SiC LDMOS power device

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