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This paper studies comparatively the effect of annealing in O 2 , N 2 O, NO and CO 2 on interfacial electrical properties of 4H-SiC/SiO 2 using MOS capacitors and FETs. From the capacitors, interface trap density (D it ) have been extracted and the NO-annealed sample shows the least D it while the CO 2 annealed sample also shows less D it than both dry O 2 and N 2 O samples near the conduction band edge. Extracted from lateral MOSFETs, the Hall mobility is essentially the same (~60 cm 2 /V.s) among dry O 2 , CO 2 , and NO samples. The main difference is the inversion electron concentration, which is at least an order of magnitude less in the dry O 2 and CO 2 samples. This infers that a high density of interfacial traps is responsible for the lower field-effect mobility. The inversion layer field-effect mobility of CO 2 annealed sample is similar to that of dry O 2 (~5 cm 2 /V.s) sample and less than that of the NO annealed sample (~25 cm 2 /V.s).

Lateral two-zone RESURF n-channel MOSFETs are demonstrated in 4H-SiC, with the improved 4H-SiC/SiO 2 interface properties by nitric oxide (NO) annealing. Two-zone RESURF has been used to achieve lower on-resistance at a specific breakdown voltage with optimized surface field. The maximum inversion layer field effect mobility achieved with NO annealing is 25cm 2 /V.s, 5x higher than that of the conventional dry re-oxidation process. The channel resistance is significantly reduced with the improved interface by NO annealing. The MOSFET is normally off with a low leakage current and threshold voltage around 3V. Large area devices with multi-finger geometry are also demonstrated with the current successfully scaled up to 140mA. The output characteristics exhibit excellent linear and saturation regions. The device blocks 930V and has a specific on-resistance of 170mΩ.cm 2 . This is the first demonstration of lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing.

Stacking fault formation sites and growth mechanisms in PiN diodes have been investigated. The diodes were fabricated on a 4H SiC wafer with a 150 µm thick nepitaxial layer and a grown p + anode. Stacking faults and their associated dislocations were examined by light emission imaging. Many of the stacking faults originate from extended string-like clusters that are present before electrical stressing and are observed at depths ranging from 10 to 100 µm below the SiC surface. Two possible mechanisms for creating these clusters are discussed: (1) nucleation of dislocation loops due to step bunching during epitaxial growth and (2) faulting of basal plane dislocations. Two alternate driving forces for stacking fault growth are also considered: mechanical stress relief and electronic energy lowering. Based on the growing behavior of the stacking faults, it is concluded that mechanical stress is responsible for the stacking fault growth.

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