Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N₂O Annealing

Abstract

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

Electrical Characteristics of SiO2 Deposited by Atomic Layer Deposition on 4H–SiC After Nitrous Oxide Anneal

“…For deposited dielectrics, a high-temperature PDA leads to the densification of the film through bonding promotion and annealing in N 2 O provides additional benefits [6], [13]. It has been demonstrated that N 2 O decomposes at high temperatures and generates N 2 , O 2 , NO, and atomic oxygen [14].…”

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

“…In addition, the introduction of nitrogen into the oxide=4H-SiC interface is widely performed to reduce the interface trap density of SiC-MOS devices. [24][25][26][27] However, for Si devices, excess nitridation has been reported to degrade hole trapping characteristics, [28][29][30][31] and studies on the effect of nitridation on hole trapping in SiC-MOS devices are few. [19][20][21][22][23] In this study, we establish a high-speed C-V method to evaluate the number of holes trapped by negative gate bias and estimate the mechanisms of trapping under stress and detrapping during V th measurement.…”

Enhanced Drain Current of 4H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure

“…In order to reduce the damage induced by RIE, sacrificial oxidation at 1100 • C for 1 h was performed. After depositing SiO 2 as a gate oxide by PECVD, N 2 O annealing at 1300 • C for 30 min was carried out to reduce the SiO 2 /SiC interface state density [14]. The thickness of the deposited oxide is 70 nm on the top plane and 45 nm on the sidewall plane, as determined by cross-sectional scanning electron microscopy.…”