A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS

Runge, Marcel; Schmeck, Dario; Scholz, Philipp; Boeck, Georg; Gerfers, Friedel

doi:10.1109/esscirc.2018.8494339

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…The individual SAR ADC presented in this work achieves one of the best efficiencies for sampling rates around 100 MS/s with the process used. Moreover, the efficiency is comparable to the designs reported in previous studies, [27][28][29] where much more advanced CMOS process nodes are used.…”

Section: Test Chip Measurementssupporting

confidence: 77%

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A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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This paper presents the design, implementation, and measurements of a 4 GS/s, 8-bit resolution, time-interleaved (TI) analog-to-digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI-ADC in the process used. An energy-efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on-chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low-voltage differential signaling interface is included to transmit the samples off-chip without any decimation. The TI-ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv-step and owing to the efficient interleaved architecture the full TI-ADC achieves a peak FOM of 171fJ/conv-step (526fJ/conv-step at Nyquist).

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Section: Test Chip Measurementssupporting

confidence: 77%

“…Reyes et al 12 Reyes et al 18 Louwsma et al 26 Runge et al 27 Kundu et al 28 T A B L E 3 TI-ADC performance summary and comparison…”

Section: This Workmentioning

confidence: 99%

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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“…A bridge capacitor can be used with a compact layout as in [8], but it requires a careful examination of the parasitics. A charge injection cell [9] eliminates the necessity for binary-scaled capacitors, but it requires a high frequency synchronous clock for the internal logic control [10]. MOS transistors have also been used as capacitors in the DAC [11], but its area is still limited by the minimum transistor size provided by the technology.…”

Section: Introductionmentioning

confidence: 99%

Small-Area SAR ADCs With a Compact Unit-Length DAC Layout

Shen

Cantatore

et al. 2022

IEEE Trans. Circuits Syst. II

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A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

Pahlavanzadeh

Karami

2023

Circuit Theory & Apps

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Summary This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

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A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS

Cited by 6 publications

References 7 publications

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Small-Area SAR ADCs With a Compact Unit-Length DAC Layout

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

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