A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider

Hu, Ang; Li, Dongsheng; Zhang, Kefeng; Liu, Lanqi; Zou, Xuecheng

doi:10.1109/tcsi.2020.2997598

Cited by 18 publications

(4 citation statements)

References 34 publications

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“…Therefore, clock multiplication from one clean reference is preferred. Elkholy et al reported a multi-output all-digital clock generator based on open-loop delta-sigma (∆Σ) fractional dividers [5], and there are high-performance dividers that can potentially be implemented for clock multiplication [6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

et al. 2023

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Section: Introductionmentioning

confidence: 99%

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

et al. 2023

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“…From a locktime perspective, AFC based on time-to-digital converter (TDC) counting can reduce the counting period and improve the locking speed significantly, but this method is mainly used in all digital phase-locked loops (ADPLL). Many AFC techniques have also been proposed in [8][9][10]. In order to strengthen the applicability of the clock generator by increasing the loop divider ratio, methods such as compressing the reference clock frequency range and expanding the divider ratio of MMD can be implemented.…”

Section: Introductionmentioning

confidence: 99%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

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“…For multi-GHz signal sampling, phase noise (PN) of the clock signal generated from the frequency synthesizer has a significant effect on the noise performance of data converters [6,7]. Frequency synthesizers based on charge pump phase-locked loops (CPPLL) with octave-range VCOs are widely adopted to satisfy the noise requirement and to cover various frequency bands [8,9,10,11,12]. Octave-range VCOs commonly suffer from a trade-off between tuning range and phase noise.…”

Section: Introductionmentioning

confidence: 99%

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Li¹,

Wang²,

Wang³

et al. 2021

IEICE Electron. Express

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This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm 2 . By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

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A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider

Cited by 18 publications

References 34 publications

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

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