A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Wang, Yun; Lee, Hyun Woo; Shin, Dongsuk; Kang, Shin Deok; Yang, Ji Yeon; Lee, Hyeng Ouk; Lee, Dong Uk; Sim, Su-Jeong; Kim, Young Ju; Choi, Won Jun; Song, Keun Soo; Shin, Sang Hoon; Choi, Hyang Hwa; Moon, Hyung Wook; Kwack, Seung Wook; Lee, Jung Woo; Choi, Young Kyoung; Park, Nak Kyu; Kim, Kwan Weon; Choi, Young Jae; Ahn, Ji Hoon; Yang, Ye Seok

doi:10.1109/isscc.2008.4523167

Cited by 12 publications

(2 citation statements)

References 5 publications

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“…However, the ADDLLs have the worse static phase error and jitter performance than the analog DLLs. The large amount of delay cells are normally deployed for wide operating frequency range and low jitter applications in ADDLLs [1], [2]. These open-loop ADDLLs are not able to track the clock skew caused by the PVT drift.…”

Section: Introductionmentioning

confidence: 99%

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique

Hung

Kao

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closedloop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm 2 .

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Section: Introductionmentioning

confidence: 99%

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique

Hung

Kao

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…To increase the bandwidth of DLL, the parameter "K" needs to be decreased. To guarantee performance in all process corners and various operating frequencies, "K" has to be a large integer number [3]. The proposed SDVS calculates the "K" value on the fly according to the process skew and the operating frequency.…”

mentioning

confidence: 99%

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Lee

Kim²,

Choi³

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.DRAM has several internal voltage levels which are VPP for driving word line, VBLP for bit line pre-charge, VCP for cell capacitor plate, VCORE for data store and VBBW for off-state bias of word line to reduce the off-leakage. These internal voltages have to be used to satisfy the data store operating and keep the charges during retention time. Therefore, it is hard to change these internal voltages for DRAM core. On the other hand, performance of peripheral circuits is closely connected with the FO3 (Fan-Out 3) delay. Therefore, the internal voltage level for peripheral circuits can be easily adapted according to the operating frequency and the process skew.Recently, application systems with DVS are being widely used to reduce power consumption. However, they did not take the process condition of DRAM into account. The proposed SDVS technique uses two parameters; one is the process skew of DRAM component and the other is the frequency of the CLK fed to DRAM. The proposed SDVS block diagram is shown in Figure 28.8.1. The SDVS generates the signals UP and DN for the voltage regulator after measuring the tRDLY in terms of the number of CLK cycles that comes from the controller. The tRDLY copies the timing delay between the CLK input and the DQ output. In case of slow skew, the signal UP is enabled. So the internal voltage for peripheral circuits (VPERI) is increased to improve the performance. Otherwise, if the operating frequency is slow enough to ignore the reduced timing margin, the SDVS maintains the previous VPERI or lowers the VPERI by the signal DN.By the help of SVDS, each DRAM can have an optimal VPERI that lowers the leakage and active standby current. The SDVS determines the VPERI during power up sequence or self-refresh exit condition. Figure 28.8.2(a) shows the relative FO3 delay distribution within a wafer.Randomly selected 450 samples are used for measurement. The slowest FO3 delay is improved by 20% when VPERI is raised from 1.1V to 1.2V. At VPERI of 1.1V, the FO3 delay variation is almost 30% even if the measured samples are from the same wafer. The more wafers fabricated,...

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Digital Delay Lock Techniques

Xanthopoulos

2009

Integrated Circuits and Systems

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Cited by 12 publications

References 5 publications

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Digital Delay Lock Techniques

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