A 0.13 μm CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

Imai, K.; Yamaguchi, Ken; Kimizuka, N.; Onishi, H.; Kudo, Tadachika; Ono, Akira; Noda, K.; Fujii, Hiroki; Ikeda, Masataka; Kazama, K.; Maruyama, Satoshi; Kuwata, T.; Horiuchi, Toshiyuki

doi:10.1109/iedm.1999.824240

Cited by 7 publications

(4 citation statements)

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“…This is because the proposed cell's data is maintained by the gate leakage current of the PFET access transistor from WL which is kept 1.2V. This is an advantage of the proposed cell over the conventional loadless 4T SRAM cell [15][16][17] which maintains the data by the subthreshold leakage current of the PFET access transistor from BL. It is to be noted that the read condition shown in Fig.…”

Section: Crossbar Array and Current Sensing System Designmentioning

confidence: 97%

“…Since this ensures the consistency of the weight optimization by the training software with the weight values stored in the 6TSRAM cells, higher inference accuracies are expected in the high-density accelerator Fig. 2 shows the loadless 4T SRAM cell whose data are sustained by the access PFETs' subthreshold leakage currents [15][16][17] or their gate leakage currents [18][19][20][21]. The cell size is reduced by 17% compared with the 6TSRAM cell (see Fig.…”

Section: Current Sense Accumulator For Sram Cellsmentioning

confidence: 99%

“…In this paper, we propose a current sensing scheme for an XNOR multiplier based on the loadless 4T SRAM cell [15][16][17][18][19][20][21] which is applied to the MAC operation in binarized neural network (BNN) inference accelerators. The current sense amplifiers for SRAM were proposed about 30 years ago [22][23][24].…”

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM

ZHU,

OHSAWA

2024

IEICE Trans. Electron.

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A binarized neural network (BNN) inference accelerator is designed in which weights are stores in loadless four-transistor static random access memory (4T SRAM) cells. A time-multiplexed exclusive NOR (XNOR) multiplier with switched capacitors is proposed which prevents the loadless 4T SRAM cell from being destroyed in the operation. An accumulator with current sensing scheme is also proposed to make the multiply-accumulate operation (MAC) completely linear and read-disturb free. The BNN inference accelerator is applied to the MNIST dataset recognition problem with accuracy of 96.2% for 500 data and the throughput, the energy efficiency and the area efficiency are confirmed to be 15.50TOPS, 72.17TOPS/W and 50.13TOPS/mm 2 , respectively, by HSPICE simulation in 32nm technology. Compared with the conventional SRAM cell based BNN inference accelerators which are scaled to 32nm technology, the synapse cell size is reduced to less than 16% (0.235m 2 ) and the cell efficiency (synapse array area/synapse array plus peripheral circuits) is 73.27% which is equivalent to the state-of-the-art of the SRAM cell based BNN accelerators.

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Section: Crossbar Array and Current Sensing System Designmentioning

confidence: 97%

Section: Current Sense Accumulator For Sram Cellsmentioning

confidence: 99%

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Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM

ZHU,

OHSAWA

2024

IEICE Trans. Electron.

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“…An innovative high-density SRAM using a loadless CMOS 4T cell was demonstrated for the first time in 1998 (1). The memory cell size was 1.9344 pm2 (1.04 pm x 1.86 pm), which was 35-50% smaller than a six-transistor cell using the same 0.18-pm CMOS technology (2,3). Previous works, however, only investigated DC characteristics of single-bit devices.…”

Section: Introductionmentioning

confidence: 96%

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

Noda

Matsui²,

Ito³

et al.

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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We have developed two schemes for improving access speed and reliability of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit line, which reduces coupling capacitance between adjacent bit lines in order to achieve high-speed readwrite operations; and triple-well shielding, which protects the memory cell from substrate noise and alpha particles. We incorporated these technologies in a 0.18-pm CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-pm2 memory cell. This macro fully functions at 400 MHz and has an access time of 2.35 ns.

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A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Takao

Kawamura

Mitani

et al. 2002

Microelectronics Reliability

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A 0.13 μm CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

Cited by 7 publications

References 0 publications

Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM

Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

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