A 0.13 μm high-performance SOI logic technology with embedded DRAM for system-on-a-chip application

Ho, H.; Steigerwalt, Michael; Walsh, B.; Doney, T.L.; Wildrick, D.; McFarland, P.A.; Benedict, J.; Bard, K.; Pendleton, D.; Lee, J.D.; Maurer, Siegfried L.; Corrow, B.; Sadana, D. K.

doi:10.1109/iedm.2001.979555

Cited by 7 publications

(4 citation statements)

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“…EDRAM on SOI is to use patterned SOI: Build the DRAM cells on bulk Si and all of the other circuits on SOI [26]. Figure 14 shows an implementation of patterned SOI [27]. In fact, we have built EDRAM macros on such films.…”

Section: Figure 12mentioning

confidence: 99%

“…As we move forward, SOI CMOS technology development is completed for the 0.13-m generation [6,20] and has been initiated for the 0.1-m generation [7,27]. These technologies are simply the highest-performance CMOS in production.…”

Section: Futurementioning

confidence: 99%

Section: Figure 15mentioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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Section: Figure 12mentioning

confidence: 99%

Section: Futurementioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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“…Cohen et al [11] introduced another approach to create patterned SOI materials by masked anneal. Compared with the above two methods, patterned separation by implantation of oxygen (SIMOX) technique [5,12,13] is more promising because of its simplicity, maturity and CMOScompatibility. However, it is very difficult to obtain highquality patterned SOI materials employing the conventional high-dose SIMOX technique due to the formation of local BOX layers with a large thickness of 400 nm in the silicon substrate.…”

Section: Introductionmentioning

confidence: 99%