A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

Zhao, Xiaoteng; Chen, Yong; Mak, Pui-In; Martins, Rui P.

doi:10.1109/tcsi.2020.3038865

Cited by 22 publications

(3 citation statements)

References 38 publications

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“…[1,2,5,23], this work achieves better jitter performance under the similar power consumption. It is worth mentioning here that an interesting single-loop fullrate bang-bang PAM-4 CDR has been presented in 28-nm CMOS [24,25] . A novel trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang CDR with excellent energy efficiency has been reported also in 28-nm CMOS [26] .…”

Section: Electrical Measurement Results Of Cdrmentioning

confidence: 99%

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Pan¹,

Luo²,

Li³

et al. 2022

J. Semicond.

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This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10−12 BER at 26 Gb/s for a 215−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

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Section: Electrical Measurement Results Of Cdrmentioning

confidence: 99%

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Pan¹,

Luo²,

Li³

et al. 2022

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…In the fast-developing information age, the transmission rate of the signal continues to grow [1,2,3,4]. However, the bandwidth-limited backplane channel produces severe high-frequency channel loss, which will cause serious Inter-Symbol-Interference (ISI) and pose challenges to the errorfree reception.…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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“…Moreover, the previous work 32 made use of a delay cell to produce the strobe point, which is hard to control and is easily affected by PVT variations. We also enhanced the technique presented in previous studies [33][34][35][36][37] to a wider frequency acquisition range in BBPD [38][39][40] to satisfy multi-standard applications. The frequency capture range in the [33][34][35][36][37] technique was limited by the clock generation concept adopted in those works.…”

Section: Introductionmentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

Self Cite

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

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A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

Cited by 22 publications

References 38 publications

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

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