A 0.15 μm DRAM technology node for 4 Gb DRAM

Kim, K.N.; Jeong, Hae-Yong; Jeong, Gitae; Cho, C.H.; Yang, Wonyoung; Sim, Jaesung; Lee, K.H.; Koh, G.H.; Ha, Daewon; Bae, Jun Seok; Lee, J.-G.; Park, B.J.

doi:10.1109/vlsit.1998.689181

Cited by 3 publications

(2 citation statements)

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“…11 show some of the critical features in the fabricated device. It is shown that the cell transistor drain contact is well aligned to the bitline with the self-aligned contact PAD technology [4]. The half-bitline pitch is 147 nm.…”

Section: B Device Processing Technologymentioning

confidence: 99%

“…As the density and the scale of integration progress aggressively toward 1-Gbit DRAM technology and beyond [3], [4], design and processing issues pertaining to the large chip size are becoming more prominent. The increased chip size and decreased feature size indicate that the on-chip processing C. Yoo is with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zürich, Switzerland.…”

Section: Introductionmentioning

confidence: 99%

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A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Yoon

Cha

Yoo³

et al. 1999

IEEE J. Solid-State Circuits

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A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-m process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

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Section: B Device Processing Technologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%