1999
DOI: 10.1109/16.760401
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Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

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Cited by 52 publications
(9 citation statements)
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“…This stress was thought to be generated during some oxidation process. 1,2) Therefore, the liner silicon nitride film could suppress the additional oxidation formed during the oxidation that followed, especially gate oxidation. However, the junction leakage reduction was not perfectly explained by the stress relaxation.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…This stress was thought to be generated during some oxidation process. 1,2) Therefore, the liner silicon nitride film could suppress the additional oxidation formed during the oxidation that followed, especially gate oxidation. However, the junction leakage reduction was not perfectly explained by the stress relaxation.…”
Section: Resultsmentioning
confidence: 99%
“…The key research field related to the STI technique was the correlation of junction leakage with the local stress at the top and bottom corners of a trench during the oxidation process. 1,2) The interface between the field oxide and the active region of a transistor is regarded as the major junction leakage path. This is the influential parameter in integrated circuits, especially in a dynamic random-access memory (DRAM).…”
Section: Introductionmentioning
confidence: 99%
“…The behavior of the STI dislocations and the effect on the junction leakage characteristics during the fabrication of dynamic random access memory (DRAM) with 0.15 m technology have been reported in Ref. [9]. In this work, we investigate the influence of STI mechanical stress on the hysteresis effect of PD SOI NMOS devices.…”
mentioning
confidence: 95%
“…Recently, defects resulting from shallow-trench-isolation (STI) mechanical stress are identified as one of main causes of anomalous off-state leakage current in complementary metal-oxide-semiconductor field-effect transistor (CMOS-FET). 1,2) The mechanical stress issue will become more significant in nano scale CMOS technologies because the channel becomes closer to the STI edge with the continuous shrinking of the active area. On the other hand, strain engineering such as the use of a SiGe source/drain (S/D) 3,4) has been widely used to improve device mobility for advanced high-speed and low-power CMOS devices.…”
Section: Introductionmentioning
confidence: 99%