A 0.2-μm 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Washio, Katsuyoshi; Ohue, E.; Shimamoto, H.; Oda, Katsuya; Hayami, R.; Kiyota, Yukihiro; Tanabe, M.; Kondô, Masao; Hashimoto, Takashi; Harada, Takashi

doi:10.1109/16.981217

Cited by 69 publications

(8 citation statements)

References 3 publications

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“…The sheet resistance should have a small temperature coefficient of resistance (TCR), and the process conditions for the N and P gates should be independent of the TCR. A small TCR can be obtained during the formation of a polysilicon resistor through layer-by-layer polysilicon formation [16]. The polysilicon initially has small grains following deposition, and impurity implantation results in the formation of an amorphous layer on the upper layer of the polysilicon.…”

Section: Keep Scheme Of Optimized Process Modulementioning

confidence: 99%

“…Impurity diffusion from heavily doped source/drain (S/D) regions during BJT block processing was adjustable until the 0.25 μm generation. Expanding the MOSFET SW length and adjusting the impurity profile of the halo regions suppress the short channel effects, so the SiGe HBT module can be integrated into the base CMOS process after MOS formation [9], [12], [16]. However, things became more difficult from the 0.18 μm generation.…”

Section: Low Thermal Budget Process For Forming Hbtsmentioning

confidence: 99%

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A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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Hitachi's SiGe BiCMOS technology, which integrates 0.18 μm CMOS and a SiGe heterojunction bipolar transistor (HBT), does not degrade MOS or bipolar performance. The BiCMOS process is divided into blocks, and the ordering of their processing is optimized so that they do not interfere with each other. Low-thermal-budget SiGe HBT formation is achieved using a minimal-moisture-desorption oxide layer, thereby avoiding disturbing the CMOS process. This technology, which can also be applied to the 0.13 μm generation, has been used for applications ranging from high-speed ones like automotive radar and 40 Gbps optical communication to consumer ones like wireless.

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Section: Keep Scheme Of Optimized Process Modulementioning

confidence: 99%

Section: Low Thermal Budget Process For Forming Hbtsmentioning

confidence: 99%

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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“…As an effort to avoid such degradation, Ge composition with double ramp was proposed, in which the position of the intermediate plateau was carefully tailored such that the emitter-side edge of W B falls within the plateau region (Washio et al, 2002). As an effort to avoid such degradation, Ge composition with double ramp was proposed, in which the position of the intermediate plateau was carefully tailored such that the emitter-side edge of W B falls within the plateau region (Washio et al, 2002).…”

Section: Ideality Factormentioning

confidence: 99%

SiGe/Si Heterojunction Bipolar Transistors and Circuits

Rieh

2011

Comprehensive Semiconductor Science and Technology

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“…However, the use of high-performance vertical bipolar transistor in BiCMOS realization makes the technology more complex and costlier. This problem can be attributed to the incompatibility of vertical bipolar junction transistor (BJT) and the complementary metal oxide semiconductor (CMOS) transistor, which results in the requirement of n+-buried layers and an epitaxial silicon layer for the vertical BJT [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A high performance charge plasma based lateral bipolar transistor on selective buried oxide

Loan¹,

Bashir²,

Rafat³

et al. 2013

Semicond. Sci. Technol.

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In this paper, we present a new structure of lateral bipolar transistor on selective buried oxide. The device does not use highly doped regions; however, it employs the concept of creating n and p type charge plasma in undoped silicon by using metal electrodes of different work functions. The proposed device is named as the selective buried oxide based bipolar charge plasma transistor (SELBOX-BCPT). An extensive 2D simulation study has revealed that the proposed SELBOX-BCPT device not only possesses all the advantages of the conventional BCPT device, but it also addresses various severe problems of the BCPT device. A significant improvement in major issues of poor cutoff frequency ( f T ), low breakdown voltage and thermal efficiency has been achieved. It has been observed that the f T has increased by ∼94.6%, the breakdown voltage by 23.47% and the device is much cooler than the conventional BCPT device. A large current gain is obtained in the proposed device and is on a par with the conventional BCPT device. Further, by using mixed-mode simulation feature of the Atlas simulator, inverting amplifiers based on SELBOX-BCPT and the conventional BCPT have been realized. A significant improvement of 15% in switching-on transient time and 25.8% in switching-off transient time has been achieved in the proposed device in comparison to the conventional BCPT device.

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A 0.2-μm 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Cited by 69 publications

References 3 publications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

SiGe/Si Heterojunction Bipolar Transistors and Circuits

A high performance charge plasma based lateral bipolar transistor on selective buried oxide

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