A 0.35μm 600V ultra-thin epitaxial BCD technology for high voltage gate driver IC

Qiao, Ming; Jiang, Feng; Yu, Yang; Yuan, Zhangyi’an; Miao, Binbin; Yang, Wenqing; Wu, Jianhua; Qian, Wensheng; Deng, Ting; Liu, Donghua; Fang, Ziquan; Duan, Wenting; Yang, Junfeng; Kong, Weiran; Zhang, Chao

doi:10.1109/ispsd.2018.8393665

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…is very critical for the electromagnetic (EM) coupling between microantennas, as well as for the microantenna quality factor, due to strong magnetically induced substrate currents [32]. Moreover, due to stringent planarization requirements, metal dummies must be inserted nearby the microantennas, thus further degrading the quality factor.…”

Section: A Fabrication Technologymentioning

confidence: 99%

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A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

Spina,

Raimondi,

Castorina

et al. 2024

IEEE Trans. VLSI Syst.

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This article presents the design of a three-channel package-scale galvanic isolation interface for SiC and GaN power switching converters. The isolation interface consists of two side-by-side co-packaged chips fabricated in a low-cost 0.32-µm bipolar CMOS-DMOS (BCD) technology and includes three isolation data channels based on RF-coupled integrated microantennas. The isolation interface provides a channel for the gate driver control, a bidirectional channel for diagnostic, and a channel for the isolated power supply control. They use on-off keying (OOK)-modulated RF carriers of 1.5, 0.5, and 1.5 GHz, respectively. The galvanic isolation interface provides a maximum signal rate of 2 and 1.9 MHz for the driver and the power control channels, respectively, whereas the diagnostic channel guarantees half-duplex bidirectional communication up to 15 MHz. Thanks to the package-scale isolation approach, both reinforced galvanic isolation and first-rate common-mode transient immunity (CMTI) are achieved. High immunity to adjacent channel crosstalk is guaranteed by using channel frequency/physical separation. To best of the authors' knowledge, this is the first implementation of a package-scale galvanic isolation interface with three independent communication channels, including a bidirectional channel, in silicon technology.

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Section: A Fabrication Technologymentioning

confidence: 99%

“…Indeed, silicon implementations are usually characterized by higher complexity than the GaN ones, since they require multichannel interface with independent communication channels. They are typically developed in standard bipolar-CMOS-DMOS (BCD) technologies on high-conductivity substrate (about 10 3 S/m) [30], [31], [32].…”

Section: Introductionmentioning

confidence: 99%

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

Spina,

Raimondi,

Castorina

et al. 2024

IEEE Trans. VLSI Syst.

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show abstract

“…Moreover, an UHV LDMOS has been widely implemented in power electronics and power management circuits. Of course, an LDMOS is often used as an ESD protection device [7][8][9]. However, the ESD ability of LDMOS is very poor due to the current crowding effect, which makes the local power of a device too high to cause device melted [1], [10,11].…”

Section: Introductionmentioning

confidence: 99%

High Reliabilities Design of Stacked Ultra-High-Voltage nLDMOSs in a 0.5-μm BCD Semiconductor Technology

Chen

2021

MCMS

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High holding voltage of the stacked circular ultra-high voltage (UHV) nLDMOS component with slightly lowered ESD ability is developed by a TSMC 0.5-μm Bipolar-CMOS-DMOS (BCD) process. The holding voltage is an important parameter concerned with the latch-up immunity in a CMOS IC. In general, the holding-voltage value of a traditional nLDMOS is much lower than the supply voltage (VDD), there has high latch-up risk. In this paper, a stacking architecture of nLDMOS transistors is used to investigate the ESD ability and latch-up immunity. From experimental results, as three nLDMOS DUTs were stacked, this component has a highest holding voltage up to 180.59-V and a relatively vigorous ESD capability under without altering the operating voltage of the DUT.

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“…In recent years, the UHV LDMOS has been implemented in power electronics, Microelectromechanical systems (MEMS) domains, power management circuits, and internet of things (IoT) applications [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. The power management circuit is also an indispensable project of the internet of things.…”

Section: Introductionmentioning

confidence: 99%

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

2019

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

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A 0.35μm 600V ultra-thin epitaxial BCD technology for high voltage gate driver IC

Cited by 8 publications

References 5 publications

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

High Reliabilities Design of Stacked Ultra-High-Voltage nLDMOSs in a 0.5-μm BCD Semiconductor Technology

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

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