A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback

Abstract

This paper presents a 0.4-V continuous-time delta-sigma modulator for high-quality power-efficient audio applications. A new ultra-low voltage amplifier for high linearity and low power consumption is proposed by exploring class-AB topology with a novel local common-mode-feedback loop. A low V T self-body-biased PMOS switch is employed in feedback digital-to-analog converter to improve the linearity performance against PVT-induced on resistance variation, which avoids clock boosting that may harm long-term reliability. A simple and robust non-overlapping clock generation circuit is proposed for high SNDR performance of modulator at 0.4-V or below. Fabricated in a 130-nm CMOS process, the modulator achieves 90.2 dB signal-to-noise-plus-distortion ratio (SNDR) with 0.2 pJ/step Figure-of-Merit (FoM) over a 20-kHz signal bandwidth, outperforming the reported audio delta-sigma modulators operating at 0.5-V or below. Furthermore, the modulator can operate with a supply down to 0.34-V while achieving an 86.1 dB SNDR at 0.17 pJ/step.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

“…Eng 2023, 4, FOR PEER REVIEW 17 the silicon area if resistors R >> ro1||ro2 are required to achieve maximum Kenh values. Ultra high gain op-amps [39], Bulk driven and multistage operational amplifiers [29,35,45], rail-to-rail sample and hold circuits [18], buffers for high-density microelectrode arrays [24], LDOs [27], delta-sigma modulators [34], VGAs [36], gain and GB improved common mode feedback networks used in fully differential op-amps [30], etc. Other possible applications include the implementation of high frequency, high Q bandpass amplifiers using inductive common mode feedback (Figure 16c) where resistors are replaced by inductors and capacitors Ca, Cb by varactors CL to achieve tunable resonant frequencies ωres = 1/(LCL) 1/2 in a multistage feedforward configuration similar to the one shown in Figure 13.…”

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

“…Since the CM output is around V DD/ 2, the design of a CMFB circuit remains a challenge for the ULV amplifier. We propose a CMFB circuit with a local feedback loop which is modified from the one in [31] to provide an effective CMFB design for ULV operation. It consists of an inverting amplifier, the class-AB output stage, a resistor pair of R CM1 and R CM2 for the output CM voltage detection, and a pair of small capacitors C CM1 and C CM2 to stabilize the loop.…”