A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS

Flip-flops are essential building blocks of sequential digital circuits, but typically occupy a substantial proportion of chip area and consume significant amounts of power. This work proposes 18TSPC, a new topology of fully-static contention-free Single-Phase Clocked (SPC) Flip-Flop (FF) with only 18 transistors, the lowest number reported for this type. Implemented in 65nm CMOS, it achieves 20% cell area reduction compared to the conventional Transmission Gate FF (TGFF). Simulation results show the proposed 18TSPC is 3 times more efficient than TGFF in the Energy-Delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift-register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6V, 25 • C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

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“…5%) owing to this limitation. Recently, a True-Single-Phase-Clock FF with 18 transistors was proposed [16], shown in Fig. 2e.…”

Section: Review Of State-of-the-art Spc Ffsmentioning

confidence: 99%

“…It has [9], (b) Cross Charge-Control FF (XCFF) [13], (c) Adaptive-Coupling FF (ACFF) [14], (d) Topologically-Compressed FF (TCFF) [8] and failure mechanism [15]. (e) True-Single-Phase-Clock 18T FF (20T with Reset) [16].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Cai

Savanth

Prabhat

et al. 2019

IEEE J. Solid-State Circuits

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“…Implementing and keeping this state may consume extra electrical power and may occupy more overhead integrated circuitry layout area. Note that in addition to showing the traditional transmission gate flip-flop (TGFF), Figure 2 also includes three recently proposed low-power FF designs [28][29][30]. Figure 2b shows the adaptive coupling (AC) flip-flop design [28].…”

Section: Introductionmentioning

confidence: 99%

“…However, there are floating problems in several nodes inside this FF design, which impose limitations on the applications of the ACFF design [28]. Figure 2c shows the true single-phase clock flip-flop, named TSPCFF [29]. It is composed of a conventional dynamic TSPC-based FF design with 9 transistors colored in blue and an additional 9 transistors to ensure its static operations and sufficient output drive capability.…”

Section: Introductionmentioning

confidence: 99%

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

et al. 2020

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The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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“…Therefore, reducing flip-flop's power consumption has significant impact on whole system's energy efficiency. Many different types of flip-flops with unique topologies have been studied for achieving better efficiency of flip-flops and processors [3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Lee

2019

IEICE Electron. Express

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A novel static single-phase clocked (SSPC) dual-edge triggered flip-flop (DET-FF) is proposed to allow energy-efficient operation with aggressive voltage scaling. By employing two static latches with a singlephase clock, contention and clock phase mismatch is avoided, which significantly improves tolerance to PVT variations. The post-layout simulation performed with 28 nm CMOS technology shows that the proposed SSPC DET-FF consumes less power and has significantly better powerperformance trade off (PDP) than prior-art DET-FFs. Our Monte Carlo analysis also showed that its supply voltage can be aggressively scaled down to 0.3 V even with PVT variations.

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A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS

Cited by 34 publications

References 13 publications

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

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