A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

Hsieh, S. T.; Hsieh, Chih-Cheng

doi:10.1109/jssc.2019.2894998

Cited by 21 publications

(14 citation statements)

References 17 publications

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“…The FoM used in the comparison is computed as

Power / false(f_{s} * 2^{ENOB} false)

, where

f_{s}

is the sampling frequency. As explained in Section 3.1 this ADC circuit uses relatively large unit capacitors and contains many additional circuits to support multiple modes of operation (conventional and proposed), which unfavourably affects its FoM values when compared to some of the recent references [8, 11, 22] that are benefited with better technology and smaller unit capacitor (1.5, 0.39 and 1 fF, respectively). Nevertheless, this should not significantly undermine the validation of the proposed techniques.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…However, the dramatically reduced signal headroom in such ADCs poses a significant design challenge. A promising technique to mitigate this problem is to substitute voltage comparison by time-based comparison during bit trials [1][2][3][4][5][6][7][8][9][10][11]. Such approaches typically involve using multi-stage voltage controlled delay lines (VCDLs) to convert small voltage difference to time difference, which is then detected by phase detectors (PDs).…”

Section: Introductionmentioning

confidence: 99%

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Exploiting uncertain timing information in time‐based SAR ADCs

Wang

Nagabhushana

Leitner

2020

IET Circuits, Devices & Systems

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Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

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“…The FoM used in the comparison is computed as

Power / false(f_{s} * 2^{ENOB} false)

, where

f_{s}

Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting uncertain timing information in time‐based SAR ADCs

Wang

Nagabhushana

Leitner

2020

IET Circuits, Devices & Systems

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show abstract

“…These two functions are implemented by adding capacitors in the CDAC. To reduce the total capacitance of the CDAC that is increasing because of the boosting of the commonmode voltage and the control of the input voltage range, the proposed CDAC uses a VCM-based switching architecture [25][26][27]. To implement the single-ended SAR ADC with no dynamic range degradation although VREFT and VREFB have voltage levels corresponding to VDD and VSS, the CDAC controls the connection of the added capacitor CBOOST, as shown in Fig.…”

Section: Proposed Single-ended Asynchronous Sar With Cdac Boosting Comentioning

confidence: 99%

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

Son

Jang

2019

IEICE Electron. Express

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A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a singleended successive approximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 0.207 mm 2 and 2.29 mW, respectively. The measured DNL and INL are +0.93/−0.51 LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.

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“…MOM capacitors also take advantage of lateral electrical fields to achieve smaller area and generally larger capacitance density. In order to achieve such capacitance density, smaller parasitic capacitance and higher speed, in [7,8,9,10,11,12], MOM capacitance is used as a weighted capacitor array. In order to reduce the error introduced by weight capacitor mismatch, more and more SAR ADCs use non-binary capacitor arrays to provide redundancy for correction errors [4,7,8,9,10,13,14].…”

Section: Introductionmentioning

confidence: 99%

“…In order to achieve such capacitance density, smaller parasitic capacitance and higher speed, in [7,8,9,10,11,12], MOM capacitance is used as a weighted capacitor array. In order to reduce the error introduced by weight capacitor mismatch, more and more SAR ADCs use non-binary capacitor arrays to provide redundancy for correction errors [4,7,8,9,10,13,14]. In order to reduce the overall capacitance value and the total number of capacitors per unit, the split capacitor array becomes a capacitor array commonly used by many SAR ADCs [5,6,13,15,16], which connects different groups of capacitors with series capacitors.…”

Section: Introductionmentioning

confidence: 99%

A lateral field non-binary split weighted capacitor array based on fractal curve for SAR ADC

Zhao

Zhang

Wenxin

2020

IEICE Electron. Express

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A non-binary split-type MOM weighted capacitor array based on fractal geometry for SAR (Successive Approximation Register) ADC is proposed. By taking advantage of the geometric characteristics of the Hilbert curve, the capacitor array avoids the use of complex commoncentroid structure and complex wiring. The test results of the SAR ADC using this capacitor array show that, the measured DNL and INL were −0.26/0.38 LSBs and −0.37/0.38 LSBs, respectively. The ENOB is 8.66 bits. The SAR ADC was implemented using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 330 µm × 1190 µm and 1.89 mW, respectively.

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A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

Cited by 21 publications

References 17 publications

Exploiting uncertain timing information in time‐based SAR ADCs

Exploiting uncertain timing information in time‐based SAR ADCs

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

A lateral field non-binary split weighted capacitor array based on fractal curve for SAR ADC

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