A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

Hsieh, S. T.; Hsieh, Chih-Cheng

doi:10.1109/jssc.2018.2847306

Cited by 40 publications

(21 citation statements)

References 18 publications

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“…At 0.7V our ADC achieves the lowest FoM W which is 1.2x lower than in [1]. It is to be noted that the measured performance as shown and mentioned in [1] is after a) doing a foreground off-chip calibration (to remove multi-comparator offset) and b) performing a four-time averaged FFT, which are not performed in our measurements. In conclusion our ADC achieves the lowest reported FoM W at 0.7V, is flexible over a wide range of supply voltage and sampling frequencies with a low FoM W , and also relaxes the input drive requirements by using 175fF sampling capacitor and sampling only half of the FSIR on each C S without compromising the dynamic range.…”

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confidence: 79%

“…Fig.7 shows the SFDR/SNDR over the range of input frequencies for 0.7V(200kS/s) and 1.3V(8MS/s) operation. Table 1 compares our SAR ADCs with the lowest FoM W ADCs (< 1fJ/conv-step) [1,2]. At 0.7V our ADC achieves the lowest FoM W which is 1.2x lower than in [1].…”

mentioning

confidence: 94%

“…In comparison to the fixed delay line architecture in [1,2,7], our self-triggered delay line allows for scalability in speed wrt V DD and optimizes the energy consumption for each operating point. During sampling, the delay line is reset and the comparator CLK = 0.…”

mentioning

confidence: 99%

“…Table 1 compares our SAR ADCs with the lowest FoM W ADCs (< 1fJ/conv-step) [1,2]. At 0.7V our ADC achieves the lowest FoM W which is 1.2x lower than in [1]. It is to be noted that the measured performance as shown and mentioned in [1] is after a) doing a foreground off-chip calibration (to remove multi-comparator offset) and b) performing a four-time averaged FFT, which are not performed in our measurements.…”

mentioning

confidence: 99%

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A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

Bindra

Annema

Louwsma³

et al. 2019

2019 Symposium on VLSI Circuits

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A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm 2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias. Introduction SAR ADCs have high energy efficiency and are used in many IoT applications and low power radios. For these applications, sample rates vary from 0.1 to 10 MS/s [1-4]. ADCs achieving lowest Walden Figure-of-Merit, FoM W [1,2] reach that high energy efficiency only at a (few) fixed operating point(s). ADCs [3,4] demonstrating flexibility over supply voltage, V DD or sample rates do not achieve low FoM W. This work introduces a low FoM W SAR ADC that demonstrates flexibility in operation over V DD and sample rates. Main challenges for an energy efficient flexible SAR are: 1) kT/C and comparator noise at small V DD (or full-scale input range, FSIR) 2) distortion due to the (non-linear) sample charge associated with comparator's input and e.g. (sample) switches at large V DD (or FSIR) and 3) switching energy (CV 2) associated with the DAC. Majority voting [6] can be used to address the challenge in 1) but, at low sample rates and requires delay tuning and energy overhead in the delay line controller. Excluding comparator and switch effects, the absolute minimum sampling capacitance, C S for kT/C limited operation at a 1V P-P input for 10-bit resolution is 100fF, whereas unit cell mismatch and the non-linear (comparator) input capacitance typically requires C S to be about 250fF for < 1LSB INL/DNL for 10 bit operation [6]. This work achieves an energy-efficient flexible SAR ADC by 1) using a low noise dynamic bias comparator [5] for which the input referred noise scales with V DD to attain a near constant ENOB 2) isolating the comparator from the DAC during sampling thereby preventing distortion due to the nonlinear sample charge 3) using a C S close to the mismatch limit (175fF) and (4) using a low power self-triggered delay line. Architecture The SAR ADC uses a self-quenched dynamic bias comparator

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confidence: 79%

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confidence: 94%

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confidence: 99%

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confidence: 99%

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A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

Bindra

Annema

Louwsma³

et al. 2019

2019 Symposium on VLSI Circuits

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“…These aspects limit the maximum excursion of the input signal and affect the linearity of active analog parts, like operational amplifiers. Several researchers have struggled to improve the performances, even with the IoT constraints, by reaching a sub-femtoJoule-per-conversion-step Figure of Merit (FOM) [29][30][31][32][33][34]. Absolute FOM alone is not always the best indicator for low power conversion systems, as not all input signals require the same precision or speed (this aspect is addressed in Section 3.7).…”

Section: Io Architecturementioning

confidence: 99%

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

et al. 2019

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In today’s world, ruled by a great amount of data and mobile devices, cloud-based systems are spreading all over. Such phenomenon increases the number of connected devices, broadcast bandwidth, and information exchange. These fine-grained interconnected systems, which enable the Internet connectivity for an extremely large number of facilities (far beyond the current number of devices) go by the name of Internet of Things (IoT). In this scenario, mobile devices have an operating time which is proportional to the battery capacity, the number of operations performed per cycle and the amount of exchanged data. Since the transmission of data to a central cloud represents a very energy-hungry operation, new computational paradigms have been implemented. The computation is not completely performed in the cloud, distributing the power load among the nodes of the system, and data are compressed to reduce the transmitted power requirements. In the edge-computing paradigm, part of the computational power is moved toward data collection sources, and, only after a first elaboration, collected data are sent to the central cloud server. Indeed, the “edge” term refers to the extremities of systems represented by IoT devices. This survey paper presents the hardware architectures of typical IoT devices and sums up many of the low power techniques which make them appealing for a large scale of applications. An overview of the newest research topics is discussed, besides a final example of a complete functioning system, embedding all the introduced features.

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A 0.012‐mm² 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

Cheng,

Chen,

Stefano

et al. 2024

Circuit Theory & Apps

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SummaryThis paper proposes a true random number generator (TRNG) based on a successive approximation register (SAR) analog‐to‐digital converter (ADC). A top‐plate sampling SAR ADC structure and a new MSB‐isolation switch scheme (MISS) are combined to achieve low‐power operation and small area occupancy at the same time. When the SAR ADC has completed its conversion, a secondary firing of the comparator measures the remaining signal. This 1‐bit quantized residue serves as the true random sequence, thus eliminating the need for extra circuitry in the TRNG. A 65‐nm prototype of the proposed TRNG was found to occupy an area of 0.012 mm2 and successfully passed all the National Institute of Standards and Technology (NIST) tests without post‐processing. It achieved a figure‐of‐merit of 0.244 pJ/bit for a 1 Mb/s random sequence with a 0.8‐V power supply. Its resilience to power noise injection attacks was also verified.

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A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

Cited by 40 publications

References 18 publications

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

A 0.012‐mm² 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

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A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

Cited by 40 publications

References 18 publications

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

A 0.012‐mm2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

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A 0.012‐mm² 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor