A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS

CMOS Inverter as Analog Circuit: An Overview

“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

“…On the other hand, an AC-coupling capacitor is widely used at the input of the resistive feedback inverter, for clock buffer application [32][33][34][35][36][37][38][39] (Figure 10). The primary motivations of the AC coupling for the clock buffer are as follows:…”

A Single-ended Simultaneous Bidirectional Transceiver in 65-nm CMOS Technology

“…5(a). The voltage-mode driver employs the nMOS-nMOS type architecture to save silicon area and the swing is determined by the supply voltage V DDQ which is generated by a linear regulator [7,8].…”

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

“…However, its output common-mode (CM) level is closely coupled with output impedance. For example, when NMOS push-pull stage is employed [5], output CM level should be close to ground to allow switching operation of its pull-up NMOS transistor. As a result, it prevents receiver front-end from using high-bandwidth NMOS transistors.…”