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Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1][2][3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity. Figure 22.4.1 shows a hybrid-integration WDM receiver, with the silicon photonic IC with microring drop filters and waveguide photodetectors connected via short wirebonds to the CMOS receiver IC with the developed optical front-end circuits. Here the microring drop filters share a common bus waveguide and select a given wavelength per channel to direct onto a waveguide photodetector. In order to allow for low-complexity receive-side clocking, we develop a source-synchronous architecture with an optically forwarded clock from the WDM transmitter on one of the available wavelengths. The microring drop filters used in this work have 5μm radius and 18000 quality factor, while the waveguide photodetectors have 40fF capacitance, 0.45A/W responsivity, and 30GHz bandwidth. While this hybrid integration strategy allows for independent optimization of the photonic devices and CMOS circuits, it does add potentially a wide range of interconnect parasitics that must be compensated for in the optical front-end design.The CMOS optical receiver chip shown in Fig. 22.4.2 consists of one forwardedclock receiver channel that provides a synchronous 12GHz differential clock to the four data channels. While previously an optically-forwarded clock receiver was demonstrated at 8Gb/s with an injection-locked ring oscillator [3], at data-rates in excess of 20Gb/s the wideband clock receiver input-referred noise can induce unacceptable output jitter that is not sufficiently filtered with a wide-bandwidth ring oscillator. This design utilizes a 12GHz LC injection-locked oscillator, which allows for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Simulations show that a 12GHz 40μA inp...