A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

Iranmanesh, A.; Ilderem, V.; Biswal, Manas Ranjan; Bastani, Behnam

doi:10.1109/4.75029

Cited by 15 publications

(5 citation statements)

References 3 publications

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“…)t 2 n=l + Z Bn sin nwt (2) n=l where coefficients A, and Bn obtained by means of Fourier series analysis are given by 2 [r12 An = ~ a_r/ f(acoso)t)cosncotdt (3) 2 [rt~ B, = -~ j_r/2f(acoswt)sinnwtdt (4) T (= 2zr/w) is the period of the input signal. For an ideal linear circuit, only the fundamental component exists, i.e.…”

Section: So(t) = F(acos~ot)mentioning

confidence: 99%

“…Significant improvements in modern VLSI technologies with submicrometer feature size have motivated the design of sophisticated high-speed and high precision signal processing systems for a broader range of applications. The emphasis in circuit design has shifted from traditional bipolar and singlechannel MOS technologies to take advantage of emerging scalable CMOS and BiCMOS (Logic) technologies [2]- [6] with improved speed and driving capabilities but with reduced voltage signal handling. An important design criteria which is becoming more difficult to ascertain particularly for high-precision analog signal processing in the context of reduced supply voltage is a circuit or a system dynamic range.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Huang

Ismail

Wassenaar

1996

Analog Integr Circ Sig Process

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This paper presents a new methodology to accurately evaluate the total harmonic distortion (THD) behavior of modern integrated circuits. The methodology is general, technology independent and is used to determine large-signal or reactive THD of signal processing circuits operating in the voltage or the current domain. It is based on Fourier series analysis and Parseval's theorem, where numerical integration may be needed to accurately compute THD. For low-frequency THD, the numerical integration can be simplified to a small number of summation without degrading the accuracy. The new methodology is incorporated in a computer-aided environment which accurately estimates THD, and the speed of calculation for many circuit is several orders of magnitude faster than SPICE or other commercial CAD tools. In addition, optimization of transistor sizes to reduce THD can be achieved by incorporating the methodology in an object-oriented CAD tool such as APLAC.

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Section: So(t) = F(acos~ot)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Huang

Ismail

Wassenaar

1996

Analog Integr Circ Sig Process

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“…Not onl daes the combination of CMOS and bipolar technology into Bi&OS give the designer a wider selection of devices, it also permits the improved perhmmx in the devices themselves [8].…”

Section: Il Transistor Level Comparisonmentioning

confidence: 99%

The influence of device selection on the performance of a simple BiCMOS operational amplifier

Allen

Blalock

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems

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Abstmct -BiCMOS technology offers both the analog and digital designer a wide range of transistar selection which can be utilized to improve the puformanw of in6egretecl circuits. The tradeoffs which occur when BiCMOS is applied 00 analog circuits are examined in this paper. A simple BiCMOS op amp is used to compare the performance of all possible OOmbiaPtioos of device selections that results. A BiCMOS i q d e y t a t i o n is persently in that I. INTROWCTIONOne unique aspect of BiCMOS integrated circuit design is the availability of two distinctly different devices the MOSFET' and BIT. From the digital Peaspective, BiCMOS technology offers many advantages which must becarefull yevaluatedin a d e r to gain a performance advantage [1-4]. A simlar situation exists for the analog designer. While BiCMOS offers many opportunities, the tradeoffs in performance must be understood in order to take Theobjective of this papex is to outline b e tra&offs available to the analog designer using BiClHOS technology. While general guidelines canand will bepropoeeQ theindividual applications will makethetrpdeoffsmaecomphx. ThiswillbeillustrPtedby+nga simple op amp to analyze the performance for various select" of transistors. It w i l l be showo that the cmect sektion of transistor make salfie. This perfcnmancecomgarism isbased on simulation a l l o w e x~v e a f i c o h a r O f k d t 8~~l n thlspaper. advantage of these opportunities [J-71. ~~U~t h e~p e € f~. IL TRANSISTOR LEVEL COMPARISON Not onl daes the combination of CMOS and bipolar technology into Bi&OS give the designer a wider selection of devices, it also permits the improved perhmmx in the devices themselves [8]. An example is the lightlydoped drains of MOSFETS Probably the best way to illustrate the co * n of MOSF'ITs and bipolar devices is expressed by T * T k i s table, we have compared various Categoriesof d e v i c e p d " c e fa each type of transistm. Table 1 consists of information that is obvious and some whose impact is not so obvious. olre of the striking differences between CMOS and bipolar devices is the value of small signal t raug , Also, we note that while the turn on voltage of bipolar transistorsare less than CMOS transistors, the continual shtinkiog of MOSFETs with s d e r geometry can result in turn on volta&esanaoaching zero whiletheturnoa voltapof BJTs cannot bechaoged. ThiswouldimplythptCMosgsturptron voltagescould approach that of BJT devices. Two areas w e CMOS devices excel over bipolar devices is in the impn of an analog switch and capacitance. Si/Poly collectma Vertical and lateral PNP BJTs were available although only the lateral PNP was used in this study. Typical fT and Br for the npn wem 2GHz and 200, respeaively, while for the lateral PNP, fT was at best 25MHz and & was approximately 150 at low collector current (-LFA) with rapid rolloff at higher currents. 0 -7 8 0 3 4 5 1 0~3 .~ e1992IEEE Bipolar 05v 4 m V 4 mS 0.2-0.3V Offs&s,asymmetric 3 Gmd Table 1 -Comparison of performance categories between CMOS IIL A SIMPLE BiCMOS OP AMP In or...

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“…The driver topologies were simulated using a 0.8 pm BiCMOS process [3]. For evaluating the driver performance each gate was set up to drive a 1.5 pF capacitive load and was driven by an identical gate (FO=1.5 pF + 1 gate) in order to quantify the effects of finite input edge rates.…”

Section: Comparison Of Driver Speed and Powermentioning

confidence: 99%

A speed, power, and supply noise evaluation of ECL driver circuits

Sidiropoulos

Jouppi²,

Menon³

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

Cited by 15 publications

References 3 publications

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

The influence of device selection on the performance of a simple BiCMOS operational amplifier

A speed, power, and supply noise evaluation of ECL driver circuits

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