The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There two other research laboratories located in Palo Alto, the Network Systems Laboratory (NSL) and the Systems Research Center (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge, Massachusetts (CRL). Our research is directed towards mainstream high-performance computer systems. Our prototypes are intended to foreshadow the future computing environments used by many Digital customers. The long-term goal of WRL is to aid and accelerate the development of high-performance uni-and multi-processors. The research projects within WRL will address various aspects of high-performance computing. We believe that significant advances in computer systems do not come from any single technological advance. Technologies, both hardware and software, do not all advance at the same pace. System design is the art of composing systems which use each level of technology in an appropriate balance. A major advance in overall system performance will require reexamination of all aspects of the system. We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of higher performance systems. Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals. We publish the results of our work in a variety of journals, conferences, research reports, and technical notes. This document is a research report. Research reports are normally accounts of completed research and may include material from earlier technical notes. We use technical notes for rapid distribution of technical material; usually this represents research in progress. Research reports and technical notes may be ordered from us. You may mail your order to:

A full-custom 32b ECL microprocessor uses a l.0pm-drawn single-poly technology with four layers of aluminum and one layer of gold interconnect. The 15.4x12.6mm2 die contains 468k bipolar transistors (ft=13GHz) and 206kresistors. Figure 1 shows the chip before gold metalization and gives the floor plan. A breakdown of transistor and area usage is given in Table 1. The chip implements a subset of an existing RISC architecture [21. Hardware support for floating-point arithmetic and virtual memory is not implemented on this chip.Worst-case power dissipation with a -5.2V supply is 115W. One-mil-thick gold bus bars covering the entire chip distribute the 26A supply current (Figure 2). The low resistance of the gold bus bars is the major factor in meeting a 15mV total IR drop on each supply. The chip has 202 ECL lOOk inputs, 157 ECL lookoutputs, and254power pads. Theinnerrow ofpower pads is bonded with 1.8mil gold wires, and signals in the outer row are bonded with 1.25mil gold wires. All input pads include 50C2 terminations to a -2V supply. The chip is packaged in a 504-pin plastic PGA with decoupling capacitors in the die cavity. The chip is attached with low-modulus epoxy to a copper spreader forming the boiling surface for a thermosiphon (a heatpipe without a wick) giving a typical average junction temperature of 100°C [lJ. In normal operation, there is a temperature gradient of 25°C across the die. Figure 3 shows the package and thermosiphon.Worst-case clock frequency is 275MHz a t nominal -5.2V supply. Operation is in excess of 335MHz with a -3.9V supply.The machine has 5 pipeline stages, each one clock cycle long ( Figure 4). In instruction fetch (IF), the PC is sent to the 2kB instruction cache and the instruction at that address is read, cache tags are compared, instruction parity is checked, and the instruction is decoded. In the RD pipestage the source operands are read from the register file. 32b integer addition, subtraction, logical and shift operations, and addressing calculations take place in the ALU pipestage. In the MEM pipestage the 2kB on-chip write-through data cache is read or written. Instruction results are written to the register file and store instructions place their result in the write buffer for transfer to the external cache in the WB pipestage.A 128b bus is used for incoming data. A 64b bus Is used for outgoing data. All external data busses have byte parity. Separate address busses of 32b and 14b are used to index the external cache data and tags, respectively. Two unidirectional l l b busses are used to read and write second-level cache tags.Scan data is input on a n 8b bus and output on another 8b bus.The chip uses a single-phase differential clock. A PLL generates a l x to 8x multiple of an off-chip differential clock for use on-chip. All communication between the chip and board is synchronous. A typical external clock frequency is 80MHz. All on-chip non-RAM state devices are flip-flops with scan. U 0 pads have flip-flops clocked by the board clock. The PLL has circuitry generating s...

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Active pull-down circuits can generate less supply noise while having faster circuit delays and dissipating less power than conventional emitter follower circuits. CML or ECDL resistive pullups are quieter but have poor speed-power performance.