Clock qualification algorithm for timing analysis of custom CMOS VLSI circuits with overlapped clocking disciplines and on-section clock derivation

Menon, S.; Sakallah, Karem A.

doi:10.1109/icsi.1990.138721

Cited by 2 publications

(1 citation statement)

References 11 publications

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“…6(B)], the clock skew is defined as being negative. Negative clock skew can be used to improve the maximum performance of a synchronous system by decreasing the delay of a critical path; however, a potential minimum constraint can occur, creating a race condition [11], [12], [31], [138], [139], [145], [176], [179], [181]. In this case, when lags , the clock skew must be less than the time required for the data signal to leave the initial register, propagate through the interconnect, combinatorial logic, and setup in the final register (see Fig.…”

Section: B Minimum Data Path/clock Skew Constraint Relationshipmentioning

confidence: 99%

Clock distribution networks in synchronous digital integrated circuits

2001

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Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described, the clock distribution networks of specific industrial circuits are surveyed, and future trends are discussed.

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Section: B Minimum Data Path/clock Skew Constraint Relationshipmentioning

confidence: 99%

Clock distribution networks in synchronous digital integrated circuits

2001

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Clock Distribution In Synchronous Systems

Friedman

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are Synchronous Systems Theoretical Background of Clock Skew Timing Constraints Caused By Clock Skew Clock Distribution Design of Structured Custom Vlsi Circuits Automated Synthesis and Layout Of Clock Distribution Networks Analysis and Modeling of The Timing Characteristics of Clock Distribution Networks Specification of The Optimal Timing Characteristics of Clock Distribution Networks Example Implementations of Clock Distribution Networks Directions For Future Research In The Design Of Clock Distribution Networks Summary and Conclusions

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Clock qualification algorithm for timing analysis of custom CMOS VLSI circuits with overlapped clocking disciplines and on-section clock derivation

Cited by 2 publications

References 11 publications

Clock distribution networks in synchronous digital integrated circuits

Clock distribution networks in synchronous digital integrated circuits

Clock Distribution In Synchronous Systems

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