A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change

Abstract

Compact digital cameras require high pixel-count, high imagingperformance, and low power consumption. Pixel-size miniaturization is necessary to achieve a high pixel-count in an adequate optical format. Among CMOS image sensors, transistor-sharing techniques are widely used to make small pixels have better imaging performance [1,2,3]. The advantages of a CMOS image sensor are low power and easy system integration. Using these advantages, high-speed CMOS image sensors with on-chip ADC are developed [4,5]. High-speed imaging is one of the promising applications for CMOS image sensors.A 6.4MPixel 60frames/s CMOS image sensor is developed. The sensor is fabricated using a 0.18µm 1P3M process. Zigzag-shaped 1.75transistor/pixel architecture enables 2.5×2.5µm 2 pixels of high saturation and sensitivity. Column-parallel counter-type 10b ADCs are operated at a data rate of 432MHz enabling 6.4MPixels at 60frames/s. Moreover, a 6.4MPixel readout and 2×2 binning modes are interchangeable without insertion of an invalid frame to avoid integration-time inconsistency.Figure 27.1.1 shows the block diagram of the sensor. The sensor consists of a pixel block, a column-parallel counter-type 10b ADC, control logic, and peripheral circuits including a PLL, generating 432MHz counter clock from a 54MHz input clock. The columnparallel ADCs are composed of column-parallel comparators, counters and latches. A 10b/12b parallel LVDS interface circuit is chosen enabling data rates up to 432MHz. Figure 27.1.2 shows the pixel arrangement. A Zigzag-shaped 4-pixel sharing technique is employed. The resulting transistor count is 1.75transistor/pixel. The upper 2 pixels share the first floating diffusion. The second floating diffusion is shared by the lower 2 pixels. The first and second floating diffusion areas are connected together by wiring. A conversion gain of 40µV/e is achieved by optimizing the layout. By using zigzag-shaped sharing, an optical aperture ratio of 38% (without on-chip microlenses) and handling capacity of 12,000e at 60˚C are realized. A Bayer-pattern color filter and a microlens are fabricated on-chip. The measured quantum efficiency and sensitivity of the green pixels are 48% at 550nm and a sensitivity of 14,000e/lux*s.In this configuration, the deviation of both the Gr and Gb pixel signals becomes negligible, because the Gr and Gb photodiodes share the same transistors and the same column circuits. Moreover, the single shared unit has the same color pixels and charge summing at floating diffusion can be possible. Figure 27.1.3shows readout sequence of this sensor. The horizontal scanning time is set to 7.2µs allowing 6.4MPixels at 60frames/s. During the first period before the transfer pulse TRn, the reset level of the pixel is read out to the vertical signal line (VSL). Additionally, the ramp signal (Vcomp) is supplied to column comparators and down-counting is carried out to latch the reset level of the pixel. After transferring the signal charge (the second period), the signal level of the pixel is read out again. The ...

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

“…Because of the characteristics of the products, research with the aim of achieving a low level of noise in order to improve the image quality has become a major concern. In particular, fixed pattern noise (FPN) generated by non-uniformity of pixels and readout circuits including analog to digital converters (ADC) is a major factor causing noise in a columnparallel CMOS image sensor [1][2][3][4][5][6][7][8][9][10][11].…”

“…1(a). Although the analog CDS circuit has been widely used because it is easy to design and operate, it is difficult to improve the accuracy [5] when using this circuit because of a capacitance mismatch, a clock feedthrough error at the switch, and so on.…”

“…1(b). The two ways of conventional digital CDS -one is double memory type [1] and the other is column-counters type [2][3][4][5][6][7] -are shown in Fig. 2.…”

“…The digital CDS or dual CDS [4][5][6][7] which uses both analog CDS and digital CDS enables the resolution of CDS to improve beyond 10-bit. Nevertheless, they also have drawbacks.…”

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

“…A gain stage before the ADC with four adjustable gains is provided. For the ADC, SAR-based [5] and ramp-based architectures [6] are combined to achieve a better area-speed trade-off. Compared with the conventional SAR architecture, the required cycle count is increased from 18 cycles to 20 cycles per sample, while ADC area is reduced 48.1%.…”