A 1.2-V Current-Mode RMS-to-DC Converter Based on a Novel Two-Quadrant Electronically Simulated MOS Translinear Loop

Abstract

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a Squarer/Divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130 nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system.

New current‐mode RMS‐to‐DC converters and four‐quadrant multiplier/divider based on VDTA

“…The current-mode RMS-to-DC converters circuits that operate in weak inversion regions [1, 9-11, 36, 37, 48], usually suffering from low bandwidth, low input dynamic range and low linearity, but also featuring certain major advantages such as low supply voltage and power dissipation. In contrast, the other group in which transistors are biased in the strong inversion region [6,7,26,41,46,47], achieves a wider input range, lower distortion and linearity error, while at the same time demanding larger consumed power and supply voltage, therefore being unsuitable for low-voltage lowpower (LV-LP) applications.…”