A 1.5 micron HCMOS III technology for fast static RAMs

Abstract

A 1.5 micron, 250 A gate technology has been developed for high performance static RAMS. This new generation technology, HCMOS 111, provides increased layout density and superior performance. A self-aligned well process sequence is used to form both p-and n-tubs. Delays in word lines and interconnections are reduced through the use of a refractory-silicide gate material. The SRAM die size is reduced by utilizing an nchannel 4-transistor memory cell with resistor loads. A graded n+ source-drain structure is employed to reduce the hot electron trapping susceptibiity o f the 1.5 micron n-channel transistor. The p+ source-drain junctions are formed without a p+ masking step. The power-speed limitations of the fully static design have been overcome through the use o f address transition detection circuitry. This technology has been applied to a 4KX4 HCMOS SRAM as an initial test vehicle.