No abstract

The physical mechanisms responsible for superior cross-talk suppression are identified in a new class of silicon-on-insulator substrate (GPSOI) that incorporates a buried metallic ground plane below the active silicon and buried oxide layers. It has been shown 111 that this technology exhibits a factor of ten reduction in cross-talk power between components through the substrate compared to existing state-of-the-art silicon-based substrates using standard s,, magnitude measurements in a microwave coplanar transmission test structure. The dominant crosstalk mechanisms are identified and compared to other existing cross-talk suppression technologies using numerical electro-magnetic simulations and lumped element compact model development.

No abstract

No abstract

A 1.5 micron, 250 A gate technology has been developed for high performance static RAMS. This new generation technology, HCMOS 111, provides increased layout density and superior performance. A self-aligned well process sequence is used to form both p-and n-tubs. Delays in word lines and interconnections are reduced through the use of a refractory-silicide gate material. The SRAM die size is reduced by utilizing an nchannel 4-transistor memory cell with resistor loads. A graded n+ source-drain structure is employed to reduce the hot electron trapping susceptibiity o f the 1.5 micron n-channel transistor. The p+ source-drain junctions are formed without a p+ masking step. The power-speed limitations of the fully static design have been overcome through the use o f address transition detection circuitry. This technology has been applied to a 4KX4 HCMOS SRAM as an initial test vehicle.