A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

Vaz, B.; Goes, J.; Paulino, Nuno

doi:10.1109/vlsic.2004.1346640

Cited by 14 publications

(8 citation statements)

References 11 publications

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“…The power reduction afforded by sharing op-amps is based on the fact that an op-amp is used only during a half clock cycle. There are two types of op-amp sharing, namely 'across two channels in a parallel pipeline ADC' [7] and 'between correlated adjacent stages' [8]. The sharing of op-amps between successive stages has some drawbacks.…”

Section: Op-amp Sharing Techniquesmentioning

confidence: 99%

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

Choi

Kim

Lee

et al. 2008

Circuit Theory & Apps

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SUMMARYThis paper proposes a 10 b 25 MS/s 4.8 mW 0.13 m CMOS analog-to-digital converter (ADC) for highperformance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low-voltage, low-power, and small chip area. A two-stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched-bias power-reduction techniques reduce the power consumption of the power-hungry analog amplifiers. Lownoise reference currents and voltages are implemented on chip with optional off-chip voltage references for low-power system-on-a-chip applications. An optional down-sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 m 1P8M CMOS technology demonstrates a measured peak differential non-linearity and integral non-linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal-tonoise-and-distortion ratio and spurious-free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8mm 2 consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply.

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Section: Op-amp Sharing Techniquesmentioning

confidence: 99%

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

Choi

Kim

Lee

et al. 2008

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…At a low voltage supply, these floating switches may encounter poor conduction or even turn off since none of the transmission MOS in a switch will turn on. lent works concerning low-voltage sampling circuits have been proposed [6], [9]- [11], [14], [15]. Figure 1(b) shows a charge-redistribution S/H architecture which is commonly employed in low-voltage systems based on switched-opamp architecture [14], [15].…”

Section: Low-voltage S/h Design Issuesmentioning

confidence: 99%

“…a) E-mail: petero@spic.ee.ncku.edu.tw DOI: 10.1093/ietele/e91-c.9.1480 fore suitable for low-voltage applications [6], [9]- [11], [14], [15]. However, the drawbacks of SO technique such as lower circuit feedback factor and additional opamp turn-on time prohibit SO-based S/H from operating at high speed [6], [12].…”

Section: Introductionmentioning

confidence: 99%

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A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

Liu

Chang

2008

IEICE Transactions on Electronics

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This paper proposes a low-voltage high-speed sampleand-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of −67.3 dB up to 250 MSample/s and a 0.8V PP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.

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“…Hence, total OTA current consumption is (31) The product of (12), (31), and yields the total ADC amplifier power consumption. The OTA GBW is approximately that of the single-stage OTA and is given by (32) and the ADC ERBW then becomes (33) For comparable settling and GBW at reduced supply voltages, the differential Miller OTA will consume about four times the power of the gain-enhanced telescopic OTA but with twice the output swing. As a result, the best OTA choice for high ERBW and minimal power consumption is the single-stage OTA.…”

Section: Amplifier Power Consumptionmentioning

confidence: 99%

An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

Adeniran

Demosthenous

2006

IEEE Trans. Circuits Syst. I

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The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-m CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date.Index Terms-Analog-to-digital conversion, digital video broadcast-handheld (DVB-H), effective resolution bandwidth (ERBW), low-voltage circuits, pipeline analog-to-digital converter (ADC), power-efficient ADC.

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A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

Cited by 14 publications

References 11 publications

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

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