Low-power ∆Σ ADCs are required in a growing number of portable systems spanning from voice to biomedical applications. As CMOS technologies continue to evolve towards smaller geometries, new design techniques need to be developed to simplify the design of such ADCs, while improving energy efficiency and reducing die area. In this paper, these challenges are addressed by presenting a 2 nd -order SC ∆ΣΜ operating from a 0.9V supply that uses a single-phase clocking technique and a new amplifiersharing scheme. The ∆ΣΜ is fabricated in a 0.18µm CMOS process, occupies a die area of 0.06mm 2 , dissipates 0.2mW from a 0.9V supply, and provides 80dB SNDR and 83dB DR over a 10kHz BW. Figure 3.7.1 shows the scaled ∆ΣΜ architecture. A 2 nd -order noncascaded topology is chosen due to its robustness against non-idealities. The coefficients gx1, gx2, gdac1, gdac2 are, 1/4, 1/2, 1/3, and 1/3, respectively. The differential reference voltage, V REF , is equal to 0.75V and is defined by V REFp =0.875V and V REFn =0.125V. The OSR is 256 and the nominal clock frequency, f CLK , is 5.128MHz. The integrator (INT) outputs are designed for a differential voltage range of 1V pp , as shown in Fig. 3.7.1. The INTs are realized using a switched-opamp (SO) technique and two clockbootstrapping (CBT) circuits are used at the input switches to enhance the linearity of the input sampling SC network, since the modulator input is operated at a common-mode (CM) voltage of V DD /2. Two half-delay D-type FFs are used in the ∆ΣΜ feedback path in order to compensate for the effect of the SO half-delay INTs on the ∆ΣΜ transfer function. All coefficients are optimized to avoid the need of using any input CM dc-shifting capacitors, resulting in lower kT/C noise.The block diagram of the fully differential ∆ΣΜ circuit is shown in Fig. 3.7.2. Traditionally, 4 non-overlapping clock phases are used to drive the SC network in the INTs [1]. In this circuit, a single-phase clock, Φ 1 , is used to drive all switches that are controlled by phases Φ 2 , Φ 2D and Φ 1D . Likewise, switches driven by phases Φ 1 , Φ 1D , and Φ 2D are driven by a complementary phase Φ 1 . Phases Φ 1 and Φ 1 are overlapping phases and, consequently, there is a certain fraction of time during which several switches conduct at the same time. This will produce a certain amount of charge that is lost when the charge is redistributed from the sampling and feedback capacitors into the integrating capacitors. However, as theoretically shown in [2], as long as the fall/risetime delay, td, of the phases and the average equivalent conductance of the switches (g AVG ) during this overlapping time are both made small, the sampled signal degradation due to having various switches conducting simultaneously is negligible. With the evolution of CMOS technologies, the values of td and g AVG are progressively being reduced. Hence, non-overlapping guard times might no longer be required in many SC circuits.In practical CBT circuits, there is always an inherent delay between the input clock phase and the g...
