16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Vaz, B.; Lynam, Adrian; Verbruggen, Bob; Laraba, A.; Mesadri, Conrado; Boumaalif, Ali; McGrath, John; Kamath, Umanath; Torre, Ronnie De Le; Manlapat, Alvin; Breathnach, Daire; Erdmann, Christophe; Farley, Brendan

doi:10.1109/isscc.2017.7870368

Cited by 48 publications

(11 citation statements)

References 2 publications

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“…IGE correction is achieved by solving (5) with Dbe and the estimated IGE coefficients. Traditionally, it is implemented according to…”

Section: Inter-stage Gain Error Correctionmentioning

confidence: 99%

“…Directly implementing root solving formula is another way, but the square root operation might be too complicated to implement. Newton iteration is applied to solve (5).Taking Dbe / k 1 as the initial value, practically, one iteration is sufficient to approach the desired Dbe.…”

Section: Inter-stage Gain Error Correctionmentioning

confidence: 99%

“…Pipeline ADCs have been widely applied to various scenarios for its potential in high resolution and high speed simultaneously [1]- [5]. However, the inter-stage gain error (IGE) restricts resolution improvement as it varies with process, voltage and temperature (PVT) [6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Yang

Yin

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a correlation-based 3 rd -order inter-stage gain error background calibration technique for high-performance pipeline ADCs, with the reduced signal swing overhead to only 8% during the pseudo noise (PN) sequence injection. This is achieved by exploiting the use of paired comparators along with a dedicated calibration algorithm, namely the adaptive dither injection calibration (ADIC) technique, which further alleviates the trade-off between the signal-to-noise ratio and the non-linearity. Monte Carlo simulation results of a 16-bit 100MS/s ADC show that with an amplifier of 20dB loop gain, the spurious-free dynamic range (SFDR) is improved from 64.8dB to a mean value of 106.6dB and a standard deviation of 1.1dB.

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“…IGE correction is achieved by solving (5) with Dbe and the estimated IGE coefficients. Traditionally, it is implemented according to…”

Section: Inter-stage Gain Error Correctionmentioning

confidence: 99%

Section: Inter-stage Gain Error Correctionmentioning

confidence: 99%

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Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Yang

Yin

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Beyond lowering the entry barrier through improved tools, Xilinx has increased FPGA utility for expanding RF sectors including 5G/6G wireless by incorporating wide bandwidth analog devices into FPGAs to create products such as the Xilinx RF System on a Chip (RFSoC). The RFSoC targeted in this work incorporates 4 GSPS ADCs and DACs into the Zynq Ultrascale+ architecture [12]. This advancement eliminates the need for separate analog devices and infrastructure circuitry reducing power consumption and device footprint around 50% [13], [14].…”

Section: Introductionmentioning

confidence: 99%

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

Bailey

Tuthill

Stefanazzi

et al. 2021

IEEE Open J. Circuits Syst.

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Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below −60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design. INDEX TERMS Adaptive computing systems with FPGA components, array signal processing, filter bank theory and design, high-level synthesis, high-performance computing and communication systems, ultra-wideband (UWB) communications.

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“…This comes at the expense of increased power consumption due to the high gain and wide bandwidth requirements of these amplifiers. Alternatively, offset compensation schemes have been presented, in the form of adding digitally-controllable capacitors at the comparator outputs [18][19][20]. Further, several charge-pump implementations with extra logic and biasing voltages [21][22][23] have been proposed.…”

Section: Introductionmentioning

confidence: 99%

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Cited by 48 publications

References 2 publications

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Cited by 48 publications

References 2 publications

Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Contact Info

Product

Resources

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Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs