A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

Abo, Andrew; Gray, P.R.

doi:10.1109/4.760369

Cited by 828 publications

(276 citation statements)

References 15 publications

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“…Comparing (18) and (19), it is seen that the C u1 for the segmented DAC is 2 kÀ1 times lower than that of the conventional DAC. For the poly-insulator-poly (PIP) capacitor in 0.35-lm CMOS process, K r ¼ 0:45 % lm and K c ¼ 0:86 fF=l m 2 .…”

Section: First-stage Sar Adc Implementationmentioning

confidence: 99%

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A pipelined SAR ADC with gain-stage based on capacitive charge pump

Chen

Alvandpour

2016

Analog Integr Circ Sig Process

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This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-lm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 lW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR [75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm 2 .

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Section: First-stage Sar Adc Implementationmentioning

confidence: 99%

“…For the input sampling switch S 1 in Fig. 1, the conventional bootstrapped switch [19] is used for improved linearity. Simulation results indicate a linearity corresponding to 17.6-bit for S 1 with a sampling capacitance of 20 pF and 20 kS/s sampling frequency which is sufficient for the 14-bit resolution.…”

Section: First-stage Sar Adc Implementationmentioning

confidence: 99%

A pipelined SAR ADC with gain-stage based on capacitive charge pump

Chen

Alvandpour

2016

Analog Integr Circ Sig Process

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“…Therefore, the actual correction will be implemented in the analog domain, preventing additional power consumption. The implementation of the controllable T&H is visualized in Figure 13: the sampling capacitors are driven by clock-boosted switches [15] and are followed by a degenerated differential pair acting as an output buffer. Each T&H has three 8-bit digitally programmable parameters: the two current sources I a and I b of the differential pair and the delay of the clock buffer.…”

Section: Analog Correction Methodsmentioning

confidence: 99%

Analog calibration of channel mismatches in time‐interleaved ADCs

Harpe

Hegt

Roermund

2008

Circuit Theory & Apps

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SUMMARYThis paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADCs. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, which minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.

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“…Prior to this work, power considerations based on a linearmodel have been reported [1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design.…”

Section: Introductionmentioning

confidence: 99%

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter

Ito

Ueno

Kurose

et al. 2005

IEICE Electron. Express

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Abstract:The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter (ADC). Prior to this work, power considerations based on a linearmodel have been reported [1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5 bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105 mW was achieved.

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A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

Cited by 828 publications

References 15 publications

A pipelined SAR ADC with gain-stage based on capacitive charge pump

A pipelined SAR ADC with gain-stage based on capacitive charge pump

Analog calibration of channel mismatches in time‐interleaved ADCs

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter

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