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This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .

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A 10-bit 1.2GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45mW from 1.2V power supply with a SNDR of 50dB and SFDR of 60dB. The proposed ADC core occupies an active area of 0.84mm 2 , and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate. Keywords: Analog-to-digital converter (ADC), Time-interleaved ADC, successive-approximation-register (SAR) ADC, Meta-stability restrained, High-linearity, Background calibration. Classification: Analog integrated circuits [11] Sunghyuk Lee, Anantha P. Chandrakasan and Hae-Seung Lee, "A 1GS/s 10b 18.9mW time-Interleaved SAR ADC with background timing skew calibration", IEEE J.

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