Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Abstract

This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .

A pipelined SAR ADC with gain-stage based on capacitive charge pump

“…where b ¼ 2 rÀN 1 is the feedback factor with the gain reduction factor r and De ¼ 1 bA ¼ 1 2 NÀN 1 is the gain error caused by the finite open-loop DC gain of the OTA [14]. In order to obtain the same voltage gain by using the CCP architecture, m charge pump stages should be connected in series.…”

“…By using A ¼ 2 NÀr [14] and (13) Following the analysis in [18], the power consumption for a single-stage transconductance amplifier with capacitive feedback is …”

“…Since the basic CCP cell can provide a gain of 2 [13], m-stage CCP can be connected in series to achieve a gain of 2 m . Combining the gain reduction solution as shown in [14], three-stage CCP was utilized to achieve a stage gain of 8. Since the gain reduction solution requires increased sampling capacitance for the second stage sub-ADC to compensate for the reduced signal swing [8], the attenuation DAC [15] was chosen to alleviate the increased capacitance requirement in the second stage.…”

“…Hence the SAR ADC with segmented binary-weighted capacitive DAC serves as the first stage in order to relax the unit capacitor value and the active chip area. The multistage CCP works as the gain-stage to amplify the residue signal with a inter-stage gain of 2 m where the m ¼ N 1 À r and r is the gain reduction factor [14]. Since the basic CCP cell applies an ideal gain of 2 [13], N 1 À r stages are necessary to achieve a gain of 2 N 1 Àr .…”

“…Since the basic CCP cell applies an ideal gain of 2 [13], N 1 À r stages are necessary to achieve a gain of 2 N 1 Àr . The inter-stage gain is reduced by 2 r times, which means an extra capacitor C x ¼ ð2 rÀ1 À 1ÞC tot2 is required for the second stage DAC [14] to compensate for the reduced signal swing where the C tot2 represents the total capacitance of second DAC. So the SAR ADC with split binary-weight capacitive DAC is chosen to alleviate the increased capacitance requirement in the second stage.…”