A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter

Abo, Andrew; Gray, P.R.

doi:10.1109/vlsic.1998.688071

Cited by 57 publications

(34 citation statements)

References 17 publications

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“…In addition to increasing the supply voltage to 1.5 V, the bias current has to be tripled to achieve the 14-MS/s sampling rate. This increases the power consumption to 8.2 mW, which is still very low compared to the 36 mW achieved in [104] with the same supply voltage and sampling rate. The measured performance is summarized in Table 12.4.…”

Section: Resultsmentioning

confidence: 91%

“…The interstage gain makes it possible to scale the components along the pipeline, which leads to low power consumption. In addition, the switched capacitor technique-with some modifications-has shown itself to be capable of very low-voltage operation [104,2]. This will be demonstrated with two prototypes [8,2] in Chapter 12.…”

Section: A/d Converters: Summarymentioning

confidence: 99%

“…Four mechanisms which can degrade a MOS device over time or suddenly destroy it are gate oxide breakdown, gate-induced drain leakage, hot-electron effects, and punch-through [104]. The first one is the result of too-high gate-source voltage, the second of too-high gate-drain voltage, and the last two of too-high drain-source voltage.…”

Section: Bootstrapped Switchesmentioning

confidence: 99%

“…A practical implementation of the bootstrapped switch is shown in Figure 6.17 [135,104]. There, the offset voltage is realized with the capacitor C1, which is precharged to V DD during the main switch off-period.…”

Section: Circuits From the Literaturementioning

confidence: 99%

“…The implementation used, e.g. in [104], consists of a latch stage preceded by coupling capacitors that are precharged to the reference voltages during the reset phase. In the acquisition phase the latch input experiences a voltage that is the sum of the input and the reference; as a result, the comparator decision level is equal to the reference voltage.…”

Section: Comparatormentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Resultsmentioning

confidence: 91%

Section: A/d Converters: Summarymentioning

confidence: 99%

Section: Bootstrapped Switchesmentioning

confidence: 99%

Section: Circuits From the Literaturementioning

confidence: 99%

Section: Comparatormentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sarafi

A’ain

Abbaszadeh

2015

Circuits Syst Signal Process

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Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 μm CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of −78.81 and −62.99 dB in 100 MS/s at V dd = 1 Volt and 50 MS/s at V dd = 0.8 V, respectively.

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A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

Heedley

Dyer

Matthews

et al. 2008

Analog Integr Circ Sig Process

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An 8-b pipelined ADC constructed in 0.13-lm CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125 MS/s while consuming 30 mW from 1.8-V and 1.2-V supplies. Active area is 0.4 mm 2 . Numerous challenges associated with this choice of process technology were overcome, such as limited dynamic range, copper metallization and the effects of gate oxide leakage.

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A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter

Cited by 57 publications

References 17 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

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