A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a 7T Dynamic Residue Amplifier

Kim, Hyeonsik; Kim, Seonkyung; Kim, Jintae

doi:10.1109/lssc.2022.3166753

Cited by 1 publication

(3 citation statements)

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“…shows key building blocks in the presented differential-gain replica. A seven-transistor DA is used as a Ref-DA [28], which is also used in the 2 nd and 3 rd stage of the ADC. To realize a four-input comparator, a differentialdifference preamplifier with a composite load consisting of a diode-connected and a cross-coupled device is utilized.…”

Section: B Differential-gain Replica Biasingmentioning

confidence: 99%

“…Therefore, we utilize a seven-transistor DA structure as shown in Fig. 7-(b), where a pair of crosscoupled transistors cancels differential kickback noise [28]. With total only 5-bit resolution from stage 3 and stage 4, the DA gain error variation up to 3% can be tolerated, which can be met by the proposed gain replica technique.…”

Section: Adc Architecture and Implementationmentioning

confidence: 99%

“…Finding accurate bit-weights in multi-stage ADCs by injecting pseudo-random noise is a traditional background calibration technique and has been successfully applied to the interstage gain calibration of the pipelined SAR ADC [24][25][26]. A foreground calibration with novel analog circuit techniques to maintain the inter-stage gain over the temperature variation has shown performance robustness over temperature [27,28].…”

Section: Introductionmentioning

confidence: 99%

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A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

2023

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This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replicabiased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.INDEX TERMS Analog-to-digital converter (ADC), pipelined successive approximation resister (SAR), dynamic amplifier, replica-biasing.

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Section: B Differential-gain Replica Biasingmentioning

confidence: 99%

Section: Adc Architecture and Implementationmentioning

confidence: 99%