A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration

Berny, A.D.; Niknejad, Ali M.; Meyer, Robert G.

doi:10.1109/jssc.2004.842851

Cited by 301 publications

(117 citation statements)

References 18 publications

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“…To mitigate the variations in VCO phase noise, automatic amplitude control techniques have been previously presented [9]- [11]. The goal of these control loops is to keep the oscillation amplitude constant across process, temperature, and frequency using an on-chip peak detector.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

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Section: Measurement Resultsmentioning

confidence: 99%

“…This range covers operation over 22. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. 4 GHz, with margin, meeting requirements for a 60-GHz superheterodyne radio [2].…”

mentioning

confidence: 99%

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…A cross-coupled PMOS pair ( and ) is used to improve the phase noise performance in the region. In order to accomplish a wideband tuning range with relatively low VCO gain (resulting in low phase noise), a two-step frequency tuning mechanism is adopted [23]. The first coarse tuning is fulfilled by 2-bit binary-weighted MIM capacitors ( and ) in the LC tank.…”

Section: Voltage-controlled Oscillator (Vco)mentioning

confidence: 99%

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

Jeon

Wang

et al. 2008

IEEE J. Solid-State Circuits

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Abstract-This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.

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“…By controlling the on/off of the parallel transistors, the effective resistance of the STTA establishes the biasing current of the VCO. The configuration of the transistor array can be determined through a control loop, where either current detection or the output voltage swing detection [10] can be performed to determine the optimum transistor array settings. The VCO buffer immediately following the VCO also affects the phase noise significantly; therefore, the same biasing scheme is also applied.…”

Section: -Ghz Pll Implementationsmentioning

confidence: 99%